aboutsummaryrefslogtreecommitdiff
path: root/toolruns/Makefile
diff options
context:
space:
mode:
authorJoachim StroĢˆmbergson <joachim@secworks.se>2014-04-05 14:09:21 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2014-04-05 14:09:21 +0200
commit48a8952394981b2ba627e349108d124792e46302 (patch)
tree04b35ec40b379aa3a8ea8174eee6e9260e8a3b7a /toolruns/Makefile
parentcaeee536cf406af4be5340227bda87792cc59858 (diff)
Adding Makefile for building sha512 simulation targets.
Diffstat (limited to 'toolruns/Makefile')
-rwxr-xr-xtoolruns/Makefile96
1 files changed, 96 insertions, 0 deletions
diff --git a/toolruns/Makefile b/toolruns/Makefile
new file mode 100755
index 0000000..03073ca
--- /dev/null
+++ b/toolruns/Makefile
@@ -0,0 +1,96 @@
+#===================================================================
+#
+# Makefile
+# --------
+# Makefile for building sha512 wmem, core and top simulations.
+#
+#
+# Author: Joachim Strombergson
+# Copyright (c) 2014, SUNET
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or
+# without modification, are permitted provided that the following
+# conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#===================================================================
+
+#WMEM_SRC=../src/rtl/sha256_w_mem.v
+#WMEM_TB_SRC=../src/tb/tb_sha256_w_mem.v
+
+CORE_SRC=../src/rtl/sha512_core.v ../src/rtl/sha512_h_constants.v ../src/rtl/sha512_k_constants.v ../src/rtl/sha512_w_mem.v
+CORE_TB_SRC=../src/tb/tb_sha512_core.v
+
+TOP_SRC=../src/rtl/sha512.v
+TOP_TB_SRC=../src/tb/tb_sha512.v
+
+#WB_SRC=../src/rtl/wb_sha256.v $(CORE_SRC)
+#WB_TB_SRC=../src/tb/tb_wb_sha256.v
+
+CC=iverilog
+
+
+all: top core
+
+
+#wb: $(WB_TB_SRC) $(WB_SRC)
+# $(CC) -o wb.sim $(WB_TB_SRC) $(WB_SRC)
+
+
+top: $(TOP_TB_SRC) $(TOP_SRC)
+ $(CC) -o top.sim $(TOP_TB_SRC) $(TOP_SRC) $(CORE_SRC)
+
+
+core: $(CORE_TB_SRC) $(CORE_SRC)
+ $(CC) -o core.sim $(CORE_SRC) $(CORE_TB_SRC)
+
+
+sim-top: top.sim
+ ./top.sim
+
+
+sim-core: core.sim
+ ./core.sim
+
+
+clean:
+ rm -f top.sim
+ rm -f core.sim
+ rm -f wmem.sim
+
+
+help:
+ @echo "Supported targets:"
+ @echo "------------------"
+ @echo "all: Build all simulation targets."
+ @echo "top: Build the top simulation target."
+ @echo "core: Build the core simulation target."
+ @echo "sim-top: Run top level simulation."
+ @echo "sim-core: Run core level simulation."
+ @echo "clean: Delete all built files."
+
+#===================================================================
+# EOF Makefile
+#===================================================================
+