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authorJoachim StroĢˆmbergson <joachim@secworks.se>2014-11-20 10:38:46 +0100
committerJoachim StroĢˆmbergson <joachim@secworks.se>2014-11-20 10:38:46 +0100
commitfa8db082f8f945c87abf808b3b692f367a21d159 (patch)
tree9e826884fc8dd6a0ce38364f8ff4897bd9cf2c2a /src/tb
parent884e61e8e11fa99401b39654e13f94b4a1c8ae53 (diff)
Adding work factor processing functionality.
Diffstat (limited to 'src/tb')
-rw-r--r--src/tb/tb_sha512.v334
1 files changed, 190 insertions, 144 deletions
diff --git a/src/tb/tb_sha512.v b/src/tb/tb_sha512.v
index f84ef56..c993cfc 100644
--- a/src/tb/tb_sha512.v
+++ b/src/tb/tb_sha512.v
@@ -8,30 +8,30 @@
// Author: Joachim Strombergson
// Copyright (c) 2014, SUNET
// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or
-// without modification, are permitted provided that the following
-// conditions are met:
-//
-// 1. Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// 2. Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in
-// the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
@@ -46,7 +46,7 @@
// Test module.
//------------------------------------------------------------------
module tb_sha512();
-
+
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
@@ -55,87 +55,91 @@ module tb_sha512();
parameter CLK_PERIOD = 2;
parameter CLK_HALF_PERIOD = CLK_PERIOD / 2;
-
+
// The address map.
- parameter ADDR_NAME0 = 8'h00;
- parameter ADDR_NAME1 = 8'h01;
- parameter ADDR_VERSION = 8'h02;
-
- parameter ADDR_CTRL = 8'h08;
- parameter CTRL_INIT_BIT = 0;
- parameter CTRL_NEXT_BIT = 1;
- parameter CTRL_MODE_LOW_BIT = 2;
- parameter CTRL_MODE_HIGH_BIT = 3;
- parameter CTRL_INIT_VALUE = 2'h01;
- parameter CTRL_NEXT_VALUE = 2'h02;
-
- parameter ADDR_STATUS = 8'h09;
- parameter STATUS_READY_BIT = 0;
- parameter STATUS_VALID_BIT = 1;
-
- parameter ADDR_BLOCK0 = 8'h10;
- parameter ADDR_BLOCK1 = 8'h11;
- parameter ADDR_BLOCK2 = 8'h12;
- parameter ADDR_BLOCK3 = 8'h13;
- parameter ADDR_BLOCK4 = 8'h14;
- parameter ADDR_BLOCK5 = 8'h15;
- parameter ADDR_BLOCK6 = 8'h16;
- parameter ADDR_BLOCK7 = 8'h17;
- parameter ADDR_BLOCK8 = 8'h18;
- parameter ADDR_BLOCK9 = 8'h19;
- parameter ADDR_BLOCK10 = 8'h1a;
- parameter ADDR_BLOCK11 = 8'h1b;
- parameter ADDR_BLOCK12 = 8'h1c;
- parameter ADDR_BLOCK13 = 8'h1d;
- parameter ADDR_BLOCK14 = 8'h1e;
- parameter ADDR_BLOCK15 = 8'h1f;
- parameter ADDR_BLOCK16 = 8'h20;
- parameter ADDR_BLOCK17 = 8'h21;
- parameter ADDR_BLOCK18 = 8'h22;
- parameter ADDR_BLOCK19 = 8'h23;
- parameter ADDR_BLOCK20 = 8'h24;
- parameter ADDR_BLOCK21 = 8'h25;
- parameter ADDR_BLOCK22 = 8'h26;
- parameter ADDR_BLOCK23 = 8'h27;
- parameter ADDR_BLOCK24 = 8'h28;
- parameter ADDR_BLOCK25 = 8'h29;
- parameter ADDR_BLOCK26 = 8'h2a;
- parameter ADDR_BLOCK27 = 8'h2b;
- parameter ADDR_BLOCK28 = 8'h2c;
- parameter ADDR_BLOCK29 = 8'h2d;
- parameter ADDR_BLOCK30 = 8'h2e;
- parameter ADDR_BLOCK31 = 8'h2f;
-
- parameter ADDR_DIGEST0 = 8'h40;
- parameter ADDR_DIGEST1 = 8'h41;
- parameter ADDR_DIGEST2 = 8'h42;
- parameter ADDR_DIGEST3 = 8'h43;
- parameter ADDR_DIGEST4 = 8'h44;
- parameter ADDR_DIGEST5 = 8'h45;
- parameter ADDR_DIGEST6 = 8'h46;
- parameter ADDR_DIGEST7 = 8'h47;
- parameter ADDR_DIGEST8 = 8'h48;
- parameter ADDR_DIGEST9 = 8'h49;
- parameter ADDR_DIGEST10 = 8'h4a;
- parameter ADDR_DIGEST11 = 8'h4b;
- parameter ADDR_DIGEST12 = 8'h4c;
- parameter ADDR_DIGEST13 = 8'h4d;
- parameter ADDR_DIGEST14 = 8'h4e;
- parameter ADDR_DIGEST15 = 8'h4f;
-
-
- parameter MODE_SHA_512_224 = 0;
- parameter MODE_SHA_512_256 = 1;
- parameter MODE_SHA_384 = 2;
- parameter MODE_SHA_512 = 3;
-
-
+ parameter ADDR_NAME0 = 8'h00;
+ parameter ADDR_NAME1 = 8'h01;
+ parameter ADDR_VERSION = 8'h02;
+
+ parameter ADDR_CTRL = 8'h08;
+ parameter CTRL_INIT_BIT = 0;
+ parameter CTRL_NEXT_BIT = 1;
+ parameter CTRL_MODE_LOW_BIT = 2;
+ parameter CTRL_MODE_HIGH_BIT = 3;
+ parameter CTRL_WORK_FACTOR_BIT = 7;
+
+ parameter ADDR_STATUS = 8'h09;
+ parameter STATUS_READY_BIT = 0;
+ parameter STATUS_VALID_BIT = 1;
+
+ parameter ADDR_WORK_FACTOR_NUM = 8'h0a;
+
+ parameter ADDR_BLOCK0 = 8'h10;
+ parameter ADDR_BLOCK1 = 8'h11;
+ parameter ADDR_BLOCK2 = 8'h12;
+ parameter ADDR_BLOCK3 = 8'h13;
+ parameter ADDR_BLOCK4 = 8'h14;
+ parameter ADDR_BLOCK5 = 8'h15;
+ parameter ADDR_BLOCK6 = 8'h16;
+ parameter ADDR_BLOCK7 = 8'h17;
+ parameter ADDR_BLOCK8 = 8'h18;
+ parameter ADDR_BLOCK9 = 8'h19;
+ parameter ADDR_BLOCK10 = 8'h1a;
+ parameter ADDR_BLOCK11 = 8'h1b;
+ parameter ADDR_BLOCK12 = 8'h1c;
+ parameter ADDR_BLOCK13 = 8'h1d;
+ parameter ADDR_BLOCK14 = 8'h1e;
+ parameter ADDR_BLOCK15 = 8'h1f;
+ parameter ADDR_BLOCK16 = 8'h20;
+ parameter ADDR_BLOCK17 = 8'h21;
+ parameter ADDR_BLOCK18 = 8'h22;
+ parameter ADDR_BLOCK19 = 8'h23;
+ parameter ADDR_BLOCK20 = 8'h24;
+ parameter ADDR_BLOCK21 = 8'h25;
+ parameter ADDR_BLOCK22 = 8'h26;
+ parameter ADDR_BLOCK23 = 8'h27;
+ parameter ADDR_BLOCK24 = 8'h28;
+ parameter ADDR_BLOCK25 = 8'h29;
+ parameter ADDR_BLOCK26 = 8'h2a;
+ parameter ADDR_BLOCK27 = 8'h2b;
+ parameter ADDR_BLOCK28 = 8'h2c;
+ parameter ADDR_BLOCK29 = 8'h2d;
+ parameter ADDR_BLOCK30 = 8'h2e;
+ parameter ADDR_BLOCK31 = 8'h2f;
+
+ parameter ADDR_DIGEST0 = 8'h40;
+ parameter ADDR_DIGEST1 = 8'h41;
+ parameter ADDR_DIGEST2 = 8'h42;
+ parameter ADDR_DIGEST3 = 8'h43;
+ parameter ADDR_DIGEST4 = 8'h44;
+ parameter ADDR_DIGEST5 = 8'h45;
+ parameter ADDR_DIGEST6 = 8'h46;
+ parameter ADDR_DIGEST7 = 8'h47;
+ parameter ADDR_DIGEST8 = 8'h48;
+ parameter ADDR_DIGEST9 = 8'h49;
+ parameter ADDR_DIGEST10 = 8'h4a;
+ parameter ADDR_DIGEST11 = 8'h4b;
+ parameter ADDR_DIGEST12 = 8'h4c;
+ parameter ADDR_DIGEST13 = 8'h4d;
+ parameter ADDR_DIGEST14 = 8'h4e;
+ parameter ADDR_DIGEST15 = 8'h4f;
+
+ parameter MODE_SHA_512_224 = 2'h0;
+ parameter MODE_SHA_512_256 = 2'h1;
+ parameter MODE_SHA_384 = 2'h2;
+ parameter MODE_SHA_512 = 2'h3;
+
+ parameter CTRL_INIT_VALUE = 2'h1;
+ parameter CTRL_NEXT_VALUE = 2'h2;
+ parameter CTRL_WORK_FACTOR_VALUE = 1'h1;
+
+
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
- reg [31 : 0] cycle_ctr;
- reg [31 : 0] error_ctr;
- reg [31 : 0] tc_ctr;
+ reg [31 : 0] cycle_ctr;
+ reg [31 : 0] error_ctr;
+ reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
@@ -148,36 +152,36 @@ module tb_sha512();
reg [31 : 0] read_data;
reg [511 : 0] digest_data;
-
-
+
+
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
sha512 dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
-
+
.cs(tb_cs),
.we(tb_we),
-
-
+
+
.address(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data),
.error(tb_error)
);
-
+
//----------------------------------------------------------------
// clk_gen
//
- // Clock generator process.
+ // Clock generator process.
//----------------------------------------------------------------
- always
+ always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
-
+
//----------------------------------------------------------------
// sys_monitor
@@ -191,7 +195,7 @@ module tb_sha512();
cycle_ctr = cycle_ctr + 1;
end
-
+
//----------------------------------------------------------------
// dump_dut_state()
//
@@ -202,20 +206,20 @@ module tb_sha512();
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
- $display("cs = 0x%01x, we = 0x%01x",
+ $display("cs = 0x%01x, we = 0x%01x",
dut.cs, dut.we);
$display("address = 0x%02x", dut.address);
- $display("write_data = 0x%08x, read_data = 0x%08x",
+ $display("write_data = 0x%08x, read_data = 0x%08x",
dut.write_data, dut.read_data);
$display("tmp_read_data = 0x%08x", dut.tmp_read_data);
$display("");
$display("Control and status:");
- $display("ctrl = 0x%02x, status = 0x%02x",
- {dut.next_reg, dut.init_reg},
+ $display("ctrl = 0x%02x, status = 0x%02x",
+ {dut.next_reg, dut.init_reg},
{dut.digest_valid_reg, dut.ready_reg});
$display("");
-
+
$display("Message block:");
$display("block0 = 0x%08x, block1 = 0x%08x, block2 = 0x%08x, block3 = 0x%08x",
dut.block0_reg, dut.block1_reg, dut.block2_reg, dut.block3_reg);
@@ -238,15 +242,15 @@ module tb_sha512();
dut.block28_reg, dut.block29_reg, dut.block30_reg, dut.block31_reg);
$display("");
-
+
$display("Digest:");
$display("digest = 0x%0128x", dut.digest_reg);
$display("");
-
+
end
endtask // dump_dut_state
-
-
+
+
//----------------------------------------------------------------
// reset_dut()
//
@@ -263,7 +267,7 @@ module tb_sha512();
end
endtask // reset_dut
-
+
//----------------------------------------------------------------
// init_sim()
//
@@ -275,7 +279,7 @@ module tb_sha512();
cycle_ctr = 32'h00000000;
error_ctr = 32'h00000000;
tc_ctr = 32'h00000000;
-
+
tb_clk = 0;
tb_reset_n = 0;
tb_cs = 0;
@@ -285,7 +289,7 @@ module tb_sha512();
end
endtask // init_dut
-
+
//----------------------------------------------------------------
// display_test_result()
//
@@ -304,8 +308,8 @@ module tb_sha512();
end
end
endtask // display_test_result
-
-
+
+
//----------------------------------------------------------------
// wait_ready()
//
@@ -319,14 +323,14 @@ module tb_sha512();
task wait_ready();
begin
read_data = 0;
-
+
while (read_data == 0)
begin
read_word(ADDR_STATUS);
end
end
endtask // wait_ready
-
+
//----------------------------------------------------------------
// write_word()
@@ -341,7 +345,7 @@ module tb_sha512();
$display("*** Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
-
+
tb_address = address;
tb_write_data = word;
tb_cs = 1;
@@ -394,7 +398,7 @@ module tb_sha512();
write_word(ADDR_BLOCK31, block[31 : 0]);
end
endtask // write_block
-
+
//----------------------------------------------------------------
// read_word()
@@ -420,7 +424,7 @@ module tb_sha512();
end
endtask // read_word
-
+
//----------------------------------------------------------------
// check_name_version()
//
@@ -491,7 +495,7 @@ module tb_sha512();
digest_data[31 : 0] = read_data;
end
endtask // read_digest
-
+
//----------------------------------------------------------------
// get_mask()
@@ -583,12 +587,12 @@ module tb_sha512();
$display("TC%01d: Got: 0x%0128x", tc_ctr, masked_data);
error_ctr = error_ctr + 1;
end
- $display("*** TC%01d - Single block test done.", tc_ctr);
+ $display("*** TC%01d - Single block test done.", tc_ctr);
tc_ctr = tc_ctr + 1;
end
endtask // single_block_test
-
-
+
+
//----------------------------------------------------------------
// double_block_test()
//
@@ -605,9 +609,10 @@ module tb_sha512();
);
reg [511 : 0] mask;
reg [511 : 0] masked_data1;
+ reg [31 : 0] ctrl_cmd;
begin
- $display("*** TC%01d - Double block test started.", tc_ctr);
+ $display("*** TC%01d - Double block test started.", tc_ctr);
// First block
write_block(block0);
@@ -634,7 +639,7 @@ module tb_sha512();
#(CLK_PERIOD);
wait_ready();
read_digest();
-
+
mask = get_mask(mode);
masked_data1 = digest_data & mask;
@@ -650,15 +655,53 @@ module tb_sha512();
error_ctr = error_ctr + 1;
end
- $display("*** TC%01d - Double block test done.", tc_ctr);
+ $display("*** TC%01d - Double block test done.", tc_ctr);
tc_ctr = tc_ctr + 1;
end
endtask // double_block_test
-
+
+ //----------------------------------------------------------------
+ // work_factor_test()
+ //
+ // Perform test of the work factor function.
+ //----------------------------------------------------------------
+ task work_factor_test();
+ reg [1023 : 0] my_block;
+ reg [511 : 0] my_digest;
+ reg [31 : 0] my_ctrl_cmd;
+
+ begin
+ $display("*** TC%01d - Work factor test started.", tc_ctr);
+
+ // Read out work factor number.
+ read_word(ADDR_WORK_FACTOR_NUM);
+
+ // Trying to change the work factor number.
+ write_word(ADDR_WORK_FACTOR_NUM, 32'h00000003);
+ read_word(ADDR_WORK_FACTOR_NUM);
+
+ // Set block to all zero
+ my_block = {16{64'h0000000000000000}};
+ write_block(my_block);
+
+ // Set init+ work factor. We use SHA-512 mode.
+ my_ctrl_cmd = 32'h00000000 + (CTRL_WORK_FACTOR_VALUE << 7) +
+ (MODE_SHA_512 << 2) + CTRL_INIT_VALUE;
+ write_word(ADDR_CTRL, my_ctrl_cmd);
+ #(CLK_PERIOD);
+ wait_ready();
+ read_digest();
+
+ $display("*** TC%01d - Work factor test done.", tc_ctr);
+ tc_ctr = tc_ctr + 1;
+ end
+ endtask // work_factor_test
+
+
//----------------------------------------------------------------
// sha512_test
- // The main test functionality.
+ // The main test functionality.
//
// Test cases taken from:
// http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf
@@ -670,7 +713,7 @@ module tb_sha512();
reg [511 : 0] tc2_expected;
reg [511 : 0] tc3_expected;
reg [511 : 0] tc4_expected;
-
+
reg [1024 : 0] double_block_one;
reg [1024 : 0] double_block_two;
reg [511 : 0] tc5_expected;
@@ -681,7 +724,7 @@ module tb_sha512();
reg [511 : 0] tc10_expected;
reg [511 : 0] tc11_expected;
reg [511 : 0] tc12_expected;
-
+
$display(" -- Testbench for sha512 started --");
init_sim();
@@ -700,7 +743,7 @@ module tb_sha512();
// SHA-512 single block digest and test.
tc1_expected = 512'hDDAF35A193617ABACC417349AE20413112E6FA4E89A97EA20A9EEEE64B55D39A2192992A274FC1A836BA3C23A3FEEBBD454D4423643CE80E2A9AC94FA54CA49F;
single_block_test(8'h01, MODE_SHA_512, single_block, tc1_expected);
-
+
// SHA-512_224 single block digest and test.
tc2_expected = {224'h4634270F707B6A54DAAE7530460842E20E37ED265CEEE9A43E8924AA, {9{32'h00000000}}};
single_block_test(8'h02, MODE_SHA_512_224, single_block, tc2_expected);
@@ -738,10 +781,13 @@ module tb_sha512();
tc12_expected = {384'h09330C33F71147E83D192FC782CD1B4753111B173B3B05D22FA08086E3B0F712FCC7C71A557E2DB966C3E9FA91746039, {4{32'h00000000}}};
double_block_test(8'h08, MODE_SHA_384, double_block_one, double_block_two, tc11_expected, tc12_expected);
+ // Work factor test.
+ work_factor_test();
+
dump_dut_state();
-
+
display_test_result();
-
+
$display(" -- Testbench for sha512 done. --");
$finish;
end // sha512_test