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authorJoachim StroĢˆmbergson <joachim@secworks.se>2014-09-11 17:42:34 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2014-09-11 17:42:34 +0200
commit6f28e4f30356e8e07941b9fe87a0debc26f89f8f (patch)
tree3b53454bb401354cf491d441e9eea0a8fd6c07a3 /src/rtl
parent698c12454364872584ee3d47945a2ede0f89f2c4 (diff)
Changed to asynch reset.
Diffstat (limited to 'src/rtl')
-rw-r--r--src/rtl/sha512.v4
-rw-r--r--src/rtl/sha512_core.v4
-rw-r--r--src/rtl/sha512_w_mem.v4
3 files changed, 6 insertions, 6 deletions
diff --git a/src/rtl/sha512.v b/src/rtl/sha512.v
index e3608e7..c9c388b 100644
--- a/src/rtl/sha512.v
+++ b/src/rtl/sha512.v
@@ -278,10 +278,10 @@ module sha512(
// reg_update
//
// Update functionality for all registers in the core.
- // All registers are positive edge triggered with synchronous
+ // All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
- always @ (posedge clk)
+ always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
diff --git a/src/rtl/sha512_core.v b/src/rtl/sha512_core.v
index c3a2de6..73bbcee 100644
--- a/src/rtl/sha512_core.v
+++ b/src/rtl/sha512_core.v
@@ -198,10 +198,10 @@ module sha512_core(
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
- // All registers are positive edge triggered with synchronous
+ // All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
- always @ (posedge clk)
+ always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
diff --git a/src/rtl/sha512_w_mem.v b/src/rtl/sha512_w_mem.v
index 57e6d68..47113b9 100644
--- a/src/rtl/sha512_w_mem.v
+++ b/src/rtl/sha512_w_mem.v
@@ -105,10 +105,10 @@ module sha512_w_mem(
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
- // All registers are positive edge triggered with synchronous
+ // All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
- always @ (posedge clk)
+ always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin