core/hash/sha3 - Verilog implementation sponge construction defined in the SHA-3 hash standard

Age	Commit message (Collapse)	Author
2021-06-06	The SHA-3 algorithm really wants everything to be little-endian, which is	Paul Selkirk
	at odds with everything else in our system (including the register interface to sha3_wrapper). Rather than trying to rewrite sha3, I'll isolate it in its own little-endian universe by byte-swapping all reads and writes.
2021-06-02	Change reads from clocked to unclocked to match read timing of other cores.	Paul Selkirk

2021-06-02	Reformatted	Paul Selkirk

2017-12-05	Added core wrapper.	Pavel V. Shatov (Meister)

2017-12-05	Added new testbench.	Pavel V. Shatov (Meister)

2017-12-05	Ported core to CrypTech platform	Pavel V. Shatov (Meister)
	- modified control logic (init & next flags instead of upper address bit) - registered output data bus - removed 8/16/32-bit data bus switch (we can only do 32 bits, moreover Xilinx synthesizer was too stupid to understand it)
2016-08-24	Making ModelSim happy with the testbench. Not as easy making ModelSim be ↵	Joachim Strömbergson
	friends with the sha3 core. Nor Icarus or Verilator.
2016-08-23	Writing test data into the core regs.	Joachim Strömbergson

2016-08-23	Adding functionality in sha3 tb to be able to build a baseline.	Joachim Strömbergson

2015-12-13	whack copyrights	Paul Selkirk

2015-03-13	Adding initial version of tb for sha3 core.	Joachim Strömbergson

2015-03-09	Adding initial version of sha3 core by Bernd Paysan.	Joachim Strömbergson