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2021-06-02Change reads from clocked to unclocked to match read timing of other cores.Paul Selkirk
2021-06-02ReformattedPaul Selkirk
2017-12-05Added demo program for STM32 to test the core in hardware.Pavel V. Shatov (Meister)
2017-12-05Added core wrapper.Pavel V. Shatov (Meister)
2017-12-05Added documentation.Pavel V. Shatov (Meister)
2017-12-05Added new testbench.Pavel V. Shatov (Meister)
2017-12-05Ported core to CrypTech platformPavel V. Shatov (Meister)
- modified control logic (init & next flags instead of upper address bit) - registered output data bus - removed 8/16/32-bit data bus switch (we can only do 32 bits, moreover Xilinx synthesizer was too stupid to understand it)
2016-08-24Making ModelSim happy with the testbench. Not as easy making ModelSim be ↵Joachim Strömbergson
friends with the sha3 core. Nor Icarus or Verilator.
2016-08-23Writing test data into the core regs.Joachim Strömbergson
2016-08-23Adding functionality in sha3 tb to be able to build a baseline.Joachim Strömbergson
2016-08-22Adding a makefile to start building a testbench and proper top level.Joachim Strömbergson
2015-12-13whack copyrightsPaul Selkirk
2015-03-13Adding initial version of tb for sha3 core.Joachim Strömbergson
2015-03-09Adding initial version of sha3 core by Bernd Paysan.Joachim Strömbergson
2015-03-09Adding initial version of license and readme files.Joachim Strömbergson