core/hash/sha3 - Verilog implementation sponge construction defined in the SHA-3 hash standard

Age	Commit message (Expand)	Author
2021-06-02	Change reads from clocked to unclocked to match read timing of other cores.	Paul Selkirk
2021-06-02	Reformatted	Paul Selkirk
2017-12-05	Added demo program for STM32 to test the core in hardware.	Pavel V. Shatov (Meister)
2017-12-05	Added core wrapper.	Pavel V. Shatov (Meister)
2017-12-05	Added documentation.	Pavel V. Shatov (Meister)
2017-12-05	Added new testbench.	Pavel V. Shatov (Meister)
2017-12-05	Ported core to CrypTech platform	Pavel V. Shatov (Meister)
2016-08-24	Making ModelSim happy with the testbench. Not as easy making ModelSim be frie...	Joachim Strömbergson
2016-08-23	Writing test data into the core regs.	Joachim Strömbergson
2016-08-23	Adding functionality in sha3 tb to be able to build a baseline.	Joachim Strömbergson
2016-08-22	Adding a makefile to start building a testbench and proper top level.	Joachim Strömbergson
2015-12-13	whack copyrights	Paul Selkirk
2015-03-13	Adding initial version of tb for sha3 core.	Joachim Strömbergson
2015-03-09	Adding initial version of sha3 core by Bernd Paysan.	Joachim Strömbergson
2015-03-09	Adding initial version of license and readme files.	Joachim Strömbergson