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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2017-12-05 22:20:55 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2017-12-05 22:20:55 +0300
commit9ba428e606573d233b193c8afe0ecd875866e839 (patch)
tree9194b340c247966c2d621f4715c9d1489e27c89e /src/tb
parente5fb10221c1c72292218cf718b4b6e6700924985 (diff)
Ported core to CrypTech platform
- modified control logic (init & next flags instead of upper address bit) - registered output data bus - removed 8/16/32-bit data bus switch (we can only do 32 bits, moreover Xilinx synthesizer was too stupid to understand it)
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