core/hash/sha3 - Verilog implementation sponge construction defined in the SHA-3 hash standard

Branch	Commit message	Author	Age
master	The SHA-3 algorithm really wants everything to be little-endian, which is	Paul Selkirk	4 years
sha3_mode	Add mode bits for the various flavors of SHA-3, so that the software	Paul Selkirk	4 years


Age	Commit message	Author
2021-06-07	The SHA-3 algorithm really wants everything to be little-endian, which isHEAD master	Paul Selkirk
2021-06-02	Change reads from clocked to unclocked to match read timing of other cores.	Paul Selkirk
2021-06-02	Reformatted	Paul Selkirk
2017-12-05	Added demo program for STM32 to test the core in hardware.	Pavel V. Shatov (Meister)
2017-12-05	Added core wrapper.	Pavel V. Shatov (Meister)
2017-12-05	Added documentation.	Pavel V. Shatov (Meister)
2017-12-05	Added new testbench.	Pavel V. Shatov (Meister)
2017-12-05	Ported core to CrypTech platform	Pavel V. Shatov (Meister)
2016-08-24	Making ModelSim happy with the testbench. Not as easy making ModelSim be frie...	Joachim Strömbergson
2016-08-23	Writing test data into the core regs.	Joachim Strömbergson
[...]

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https://git.cryptech.is/core/hash/sha3