core/hash/sha256 - Verilog implementation of the SHA-256 cryptographic hash function

Age	Commit message (Expand)	Author
2018-10-18	(1) Locked down API to ignore read or write requests that could leak info or ...	Joachim Strömbergson
2018-10-16	Added width definition.	Joachim Strömbergson
2016-05-31	Adding functionality to support both SHA224 and SHA256 digest modes. Note: Th...	Joachim Strömbergson
2016-05-31	Fixed long constants and instead rely on zero extend in Verilog.	Joachim Strömbergson
2015-12-13	whack copyrights	Paul Selkirk
2015-07-17	Minor cleanup.	Joachim Strömbergson
2015-07-17	Removed the address defines not needed.	Joachim Strömbergson
2015-07-17	Since state is digest having separate addresses for writing state is superflo...	Joachim Strömbergson
2015-07-16	Added logic to write state into the state registers. Simplified the state wri...	Joachim Strömbergson
2015-07-16	The digest is the complete state so we only need to be able to write back sta...	Joachim Strömbergson
2015-07-16	(1) Adding addresses to be able to read and write the internal hash state fro...	Joachim Strömbergson
2015-03-31	Revert streamlined wrapper, and don't delay register reads.	Paul Selkirk
2015-03-17	Rearrange cores.	Paul Selkirk
2014-11-07	Changed to asynch reset.	Joachim Strömbergson
2014-03-17	Removed redundant flag reset wires.	Joachim Strömbergson
2014-03-16	Adding self resetting init and next flags. Updating TBs to not reset the flag...	Joachim Strömbergson
2014-03-15	(1) Updated interface to new std. (2) Added missing input designation in task...	Joachim Strömbergson
2014-02-19	Adding top level wrapper for the sha256. This wrapper provides a simple memor...	Joachim Strömbergson