aboutsummaryrefslogtreecommitdiff
path: root/src/rtl
diff options
context:
space:
mode:
Diffstat (limited to 'src/rtl')
-rw-r--r--src/rtl/sha256.v198
-rw-r--r--src/rtl/sha256_core.v33
2 files changed, 190 insertions, 41 deletions
diff --git a/src/rtl/sha256.v b/src/rtl/sha256.v
index a7d3518..551e3b9 100644
--- a/src/rtl/sha256.v
+++ b/src/rtl/sha256.v
@@ -56,47 +56,56 @@ module sha256(
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
- parameter ADDR_NAME0 = 8'h00;
- parameter ADDR_NAME1 = 8'h01;
- parameter ADDR_VERSION = 8'h02;
-
- parameter ADDR_CTRL = 8'h08;
- parameter CTRL_INIT_BIT = 0;
- parameter CTRL_NEXT_BIT = 1;
-
- parameter ADDR_STATUS = 8'h09;
- parameter STATUS_READY_BIT = 0;
- parameter STATUS_VALID_BIT = 1;
-
- parameter ADDR_BLOCK0 = 8'h10;
- parameter ADDR_BLOCK1 = 8'h11;
- parameter ADDR_BLOCK2 = 8'h12;
- parameter ADDR_BLOCK3 = 8'h13;
- parameter ADDR_BLOCK4 = 8'h14;
- parameter ADDR_BLOCK5 = 8'h15;
- parameter ADDR_BLOCK6 = 8'h16;
- parameter ADDR_BLOCK7 = 8'h17;
- parameter ADDR_BLOCK8 = 8'h18;
- parameter ADDR_BLOCK9 = 8'h19;
- parameter ADDR_BLOCK10 = 8'h1a;
- parameter ADDR_BLOCK11 = 8'h1b;
- parameter ADDR_BLOCK12 = 8'h1c;
- parameter ADDR_BLOCK13 = 8'h1d;
- parameter ADDR_BLOCK14 = 8'h1e;
- parameter ADDR_BLOCK15 = 8'h1f;
-
- parameter ADDR_DIGEST0 = 8'h20;
- parameter ADDR_DIGEST1 = 8'h21;
- parameter ADDR_DIGEST2 = 8'h22;
- parameter ADDR_DIGEST3 = 8'h23;
- parameter ADDR_DIGEST4 = 8'h24;
- parameter ADDR_DIGEST5 = 8'h25;
- parameter ADDR_DIGEST6 = 8'h26;
- parameter ADDR_DIGEST7 = 8'h27;
-
- parameter CORE_NAME0 = 32'h73686132; // "sha2"
- parameter CORE_NAME1 = 32'h2d323536; // "-256"
- parameter CORE_VERSION = 32'h302e3830; // "0.80"
+ localparam ADDR_NAME0 = 8'h00;
+ localparam ADDR_NAME1 = 8'h01;
+ localparam ADDR_VERSION = 8'h02;
+
+ localparam ADDR_CTRL = 8'h08;
+ localparam CTRL_INIT_BIT = 0;
+ localparam CTRL_NEXT_BIT = 1;
+
+ localparam ADDR_STATUS = 8'h09;
+ localparam STATUS_READY_BIT = 0;
+ localparam STATUS_VALID_BIT = 1;
+
+ localparam ADDR_BLOCK0 = 8'h10;
+ localparam ADDR_BLOCK1 = 8'h11;
+ localparam ADDR_BLOCK2 = 8'h12;
+ localparam ADDR_BLOCK3 = 8'h13;
+ localparam ADDR_BLOCK4 = 8'h14;
+ localparam ADDR_BLOCK5 = 8'h15;
+ localparam ADDR_BLOCK6 = 8'h16;
+ localparam ADDR_BLOCK7 = 8'h17;
+ localparam ADDR_BLOCK8 = 8'h18;
+ localparam ADDR_BLOCK9 = 8'h19;
+ localparam ADDR_BLOCK10 = 8'h1a;
+ localparam ADDR_BLOCK11 = 8'h1b;
+ localparam ADDR_BLOCK12 = 8'h1c;
+ localparam ADDR_BLOCK13 = 8'h1d;
+ localparam ADDR_BLOCK14 = 8'h1e;
+ localparam ADDR_BLOCK15 = 8'h1f;
+
+ localparam ADDR_DIGEST0 = 8'h20;
+ localparam ADDR_DIGEST1 = 8'h21;
+ localparam ADDR_DIGEST2 = 8'h22;
+ localparam ADDR_DIGEST3 = 8'h23;
+ localparam ADDR_DIGEST4 = 8'h24;
+ localparam ADDR_DIGEST5 = 8'h25;
+ localparam ADDR_DIGEST6 = 8'h26;
+ localparam ADDR_DIGEST7 = 8'h27;
+
+ localparam ADDR_STATE0 = 8'h30;
+ localparam ADDR_STATE1 = 8'h31;
+ localparam ADDR_STATE2 = 8'h32;
+ localparam ADDR_STATE3 = 8'h33;
+ localparam ADDR_STATE4 = 8'h34;
+ localparam ADDR_STATE5 = 8'h35;
+ localparam ADDR_STATE6 = 8'h36;
+ localparam ADDR_STATE7 = 8'h37;
+
+ localparam CORE_NAME0 = 32'h73686132; // "sha2"
+ localparam CORE_NAME1 = 32'h2d323536; // "-256"
+ localparam CORE_VERSION = 32'h302e3831; // "0.81"
//----------------------------------------------------------------
@@ -162,6 +171,23 @@ module sha256(
wire [255 : 0] core_digest;
wire core_digest_valid;
+ wire [31 : 0] state0_rd_data;
+ reg state0_we;
+ wire [31 : 0] state1_rd_data;
+ reg state1_we;
+ wire [31 : 0] state2_rd_data;
+ reg state2_we;
+ wire [31 : 0] state3_rd_data;
+ reg state3_we;
+ wire [31 : 0] state4_rd_data;
+ reg state4_we;
+ wire [31 : 0] state5_rd_data;
+ reg state5_we;
+ wire [31 : 0] state6_rd_data;
+ reg state6_we;
+ wire [31 : 0] state7_rd_data;
+ reg state7_we;
+
reg [31 : 0] tmp_read_data;
reg tmp_error;
@@ -194,6 +220,39 @@ module sha256(
.block(core_block),
+ // State access ports
+ .H0_wr_data(write_data),
+ .H0_we(state0_we),
+ .H0_rd_data(state0_rd_data),
+
+ .H1_wr_data(write_data),
+ .H1_we(state1_we),
+ .H1_rd_data(state1_rd_data),
+
+ .H2_wr_data(write_data),
+ .H2_we(state2_we),
+ .H2_rd_data(state2_rd_data),
+
+ .H3_wr_data(write_data),
+ .H3_we(state3_we),
+ .H3_rd_data(state3_rd_data),
+
+ .H4_wr_data(write_data),
+ .H4_we(state4_we),
+ .H4_rd_data(state4_rd_data),
+
+ .H5_wr_data(write_data),
+ .H5_we(state5_we),
+ .H5_rd_data(state5_rd_data),
+
+ .H6_wr_data(write_data),
+ .H6_we(state6_we),
+ .H6_rd_data(state6_rd_data),
+
+ .H7_wr_data(write_data),
+ .H7_we(state7_we),
+ .H7_rd_data(state7_rd_data),
+
.ready(core_ready),
.digest(core_digest),
@@ -400,6 +459,15 @@ module sha256(
block13_we = 0;
block14_we = 0;
block15_we = 0;
+ state0_we = 0;
+ state1_we = 0;
+ state2_we = 0;
+ state3_we = 0;
+ state4_we = 0;
+ state5_we = 0;
+ state6_we = 0;
+ state7_we = 0;
+
tmp_read_data = 32'h00000000;
tmp_error = 0;
@@ -495,6 +563,30 @@ module sha256(
block15_we = 1;
end
+ ADDR_STATE0:
+ state0_we = 1;
+
+ ADDR_STATE1:
+ state1_we = 1;
+
+ ADDR_STATE2:
+ state2_we = 1;
+
+ ADDR_STATE3:
+ state3_we = 1;
+
+ ADDR_STATE4:
+ state4_we = 1;
+
+ ADDR_STATE5:
+ state5_we = 1;
+
+ ADDR_STATE6:
+ state6_we = 1;
+
+ ADDR_STATE7:
+ state7_we = 1;
+
default:
begin
tmp_error = 1;
@@ -651,6 +743,30 @@ module sha256(
tmp_read_data = digest_reg[31 : 0];
end
+ ADDR_STATE0:
+ tmp_read_data = state0_rd_data;
+
+ ADDR_STATE1:
+ tmp_read_data = state1_rd_data;
+
+ ADDR_STATE2:
+ tmp_read_data = state2_rd_data;
+
+ ADDR_STATE3:
+ tmp_read_data = state3_rd_data;
+
+ ADDR_STATE4:
+ tmp_read_data = state4_rd_data;
+
+ ADDR_STATE5:
+ tmp_read_data = state5_rd_data;
+
+ ADDR_STATE6:
+ tmp_read_data = state6_rd_data;
+
+ ADDR_STATE7:
+ tmp_read_data = state7_rd_data;
+
default:
begin
tmp_error = 1;
diff --git a/src/rtl/sha256_core.v b/src/rtl/sha256_core.v
index a88a359..dbcec3b 100644
--- a/src/rtl/sha256_core.v
+++ b/src/rtl/sha256_core.v
@@ -45,6 +45,39 @@ module sha256_core(
input wire [511 : 0] block,
+ // State access ports
+ input wire [31 : 0] H0_wr_data,
+ input wire H0_we,
+ output wire [31 : 0] H0_rd_data,
+
+ input wire [31 : 0] H1_wr_data,
+ input wire H1_we,
+ output wire [31 : 0] H1_rd_data,
+
+ input wire [31 : 0] H2_wr_data,
+ input wire H2_we,
+ output wire [31 : 0] H2_rd_data,
+
+ input wire [31 : 0] H3_wr_data,
+ input wire H3_we,
+ output wire [31 : 0] H3_rd_data,
+
+ input wire [31 : 0] H4_wr_data,
+ input wire H4_we,
+ output wire [31 : 0] H4_rd_data,
+
+ input wire [31 : 0] H5_wr_data,
+ input wire H5_we,
+ output wire [31 : 0] H5_rd_data,
+
+ input wire [31 : 0] H6_wr_data,
+ input wire H6_we,
+ output wire [31 : 0] H6_rd_data,
+
+ input wire [31 : 0] H7_wr_data,
+ input wire H7_we,
+ output wire [31 : 0] H7_rd_data,
+
output wire ready,
output wire [255 : 0] digest,