diff options
Diffstat (limited to 'src/rtl/sha256.v')
| -rw-r--r-- | src/rtl/sha256.v | 113 |
1 files changed, 90 insertions, 23 deletions
diff --git a/src/rtl/sha256.v b/src/rtl/sha256.v index 06ebd3d..d9acc24 100644 --- a/src/rtl/sha256.v +++ b/src/rtl/sha256.v @@ -103,8 +103,16 @@ module sha256( // Registers including update variables and write enable. //---------------------------------------------------------------- reg init_reg; + reg init_new; + reg init_we; + reg init_set; + reg init_rst; + reg next_reg; - reg ctrl_we; + reg next_new; + reg next_we; + reg next_set; + reg next_rst; reg ready_reg; @@ -233,10 +241,14 @@ module sha256( ready_reg <= core_ready; digest_valid_reg <= core_digest_valid; - if (ctrl_we) + if (init_we) begin - init_reg <= write_data[CTRL_INIT_BIT]; - next_reg <= write_data[CTRL_NEXT_BIT]; + init_reg <= init_new; + end + + if (next_we) + begin + next_reg <= next_new; end if (core_digest_valid) @@ -329,6 +341,42 @@ module sha256( //---------------------------------------------------------------- + // flag_reset + // + // Logic to reset init and next flags that has been set. + //---------------------------------------------------------------- + always @* + begin : flag_reset + init_new = 0; + init_we = 0; + next_new = 0; + next_we = 0; + + if (init_set) + begin + init_new = 1; + init_we = 1; + end + else if (init_reg) + begin + init_new = 0; + init_we = 1; + end + + if (next_set) + begin + next_new = 1; + next_we = 1; + end + else if (next_reg) + begin + next_new = 0; + next_we = 1; + end + end + + + //---------------------------------------------------------------- // api_logic // // Implementation of the api logic. If cs is enabled will either @@ -336,25 +384,28 @@ module sha256( //---------------------------------------------------------------- always @* begin : api_logic - ctrl_we = 0; - block0_we = 0; - block1_we = 0; - block2_we = 0; - block3_we = 0; - block4_we = 0; - block5_we = 0; - block6_we = 0; - block7_we = 0; - block8_we = 0; - block9_we = 0; - block10_we = 0; - block11_we = 0; - block12_we = 0; - block13_we = 0; - block14_we = 0; - block15_we = 0; + init_set = 0; + init_rst = 0; + next_set = 0; + next_rst = 0; + block0_we = 0; + block1_we = 0; + block2_we = 0; + block3_we = 0; + block4_we = 0; + block5_we = 0; + block6_we = 0; + block7_we = 0; + block8_we = 0; + block9_we = 0; + block10_we = 0; + block11_we = 0; + block12_we = 0; + block13_we = 0; + block14_we = 0; + block15_we = 0; tmp_read_data = 32'h00000000; - tmp_error = 0; + tmp_error = 0; if (cs) begin @@ -364,7 +415,23 @@ module sha256( // Write operations. ADDR_CTRL: begin - ctrl_we = 1; + if (write_data[CTRL_INIT_BIT]) + begin + init_set = 1; + end + else + begin + init_rst = 1; + end + + if (write_data[CTRL_NEXT_BIT]) + begin + next_set = 1; + end + else + begin + next_rst = 1; + end end ADDR_BLOCK0: |