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authorPaul Selkirk <paul@psgd.org>2015-03-31 16:29:42 -0400
committerPaul Selkirk <paul@psgd.org>2015-03-31 16:29:42 -0400
commitce56b11187b92572193fa9327841ad2ef2e792f8 (patch)
tree6c2c3733fe9280372b535d050bc63ba0e0a5f4dc /toolruns
parent9d5b0b9c28bfd3e5087a1481960d377ec3e47453 (diff)
Remove wishbone testbench code, because we no longer have the verilog.
Diffstat (limited to 'toolruns')
-rwxr-xr-xtoolruns/Makefile15
1 files changed, 1 insertions, 14 deletions
diff --git a/toolruns/Makefile b/toolruns/Makefile
index 4ac5f46..7cce9be 100755
--- a/toolruns/Makefile
+++ b/toolruns/Makefile
@@ -45,17 +45,10 @@ CORE_TB_SRC=../src/tb/tb_sha256_core.v
TOP_SRC=../src/rtl/sha256.v $(CORE_SRC)
TOP_TB_SRC=../src/tb/tb_sha256.v
-WB_SRC=../src/rtl/wb_sha256.v $(CORE_SRC)
-WB_TB_SRC=../src/tb/tb_wb_sha256.v
-
CC=iverilog
-all: wb top core wmem
-
-
-wb: $(WB_TB_SRC) $(WB_SRC)
- $(CC) -o wb.sim $(WB_TB_SRC) $(WB_SRC)
+all: top core wmem
top: $(TOP_TB_SRC) $(TOP_SRC)
@@ -70,10 +63,6 @@ wmem: $(WMEM_SRC) $(WMEM_TB_SRC)
$(CC) -o wmem.sim $(WMEM_SRC) $(WMEM_TB_SRC)
-sim-wb: wb.sim
- ./wb.sim
-
-
sim-top: top.sim
./top.sim
@@ -100,11 +89,9 @@ help:
@echo "Supported targets:"
@echo "------------------"
@echo "all: Build all simulation targets."
- @echo "wb: Build the Wishbone simulation target."
@echo "top: Build the top simulation target."
@echo "core: Build the core simulation target."
@echo "wmem: Build the wmem simulation target."
- @echo "sim-wb: Run top Wishbone simulation."
@echo "sim-top: Run top level simulation."
@echo "sim-core: Run core level simulation."
@echo "sim-wmem: Run wmem level simulation."