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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2019-01-08 09:55:33 +0100 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2019-01-08 09:55:33 +0100 |
| commit | caf3ad473fc5325af2146274aebe2f7c66dbd63d (patch) | |
| tree | 4ea586e35ea97dbd116a180d27036858cb293423 /src/rtl | |
| parent | d0bff25faf6cb96e0c4600cfc16eec03a78b059e (diff) | |
Ported the timing fix from SHA-512 to SHA-256. The core can now run at 170 MHz in the target FPGA.HEADmaster
Diffstat (limited to 'src/rtl')
| -rw-r--r-- | src/rtl/sha256_core.v | 2 | ||||
| -rw-r--r-- | src/rtl/sha256_w_mem.v | 9 |
2 files changed, 8 insertions, 3 deletions
diff --git a/src/rtl/sha256_core.v b/src/rtl/sha256_core.v index 048df2b..564d45e 100644 --- a/src/rtl/sha256_core.v +++ b/src/rtl/sha256_core.v @@ -564,6 +564,7 @@ module sha256_core( CTRL_ROUNDS0: begin + w_next = 1'h1; state_update = 1'h1; sha256_ctrl_new = CTRL_ROUNDS1; sha256_ctrl_we = 1'h1; @@ -572,7 +573,6 @@ module sha256_core( CTRL_ROUNDS1: begin - w_next = 1'h1; state_update = 1'h1; a_h_we = 1'h1; t_ctr_inc = 1'h1; diff --git a/src/rtl/sha256_w_mem.v b/src/rtl/sha256_w_mem.v index fef1205..40e1374 100644 --- a/src/rtl/sha256_w_mem.v +++ b/src/rtl/sha256_w_mem.v @@ -76,12 +76,14 @@ module sha256_w_mem( reg [5 : 0] w_ctr_new; reg w_ctr_we; + reg [31 : 0] w_reg; + reg [31 : 0] w_new; + //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- reg [31 : 0] w_tmp; - reg [31 : 0] w_new; //---------------------------------------------------------------- @@ -105,6 +107,7 @@ module sha256_w_mem( for (i = 0 ; i < 16 ; i = i + 1) w_mem[i] <= 32'h0; + w_reg <= 32'h0; w_ctr_reg <= 6'h0; end else @@ -129,6 +132,8 @@ module sha256_w_mem( w_mem[15] <= w_mem15_new; end + w_reg <= w_new; + if (w_ctr_we) w_ctr_reg <= w_ctr_new; end @@ -146,7 +151,7 @@ module sha256_w_mem( if (w_ctr_reg < 16) w_tmp = w_mem[w_ctr_reg[3 : 0]]; else - w_tmp = w_new; + w_tmp = w_reg; end // select_w |