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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-08-28 13:06:27 +0200 |
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| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-08-28 13:06:27 +0200 |
| commit | bb03cc0bdc9f05bdc6c861ed5d725c6a0970ae5d (patch) | |
| tree | dc0e51465e823bb19d571c83389a2ae1c89511fe /src/model | |
| parent | 0e7de630d80ad112bbb430434b6a5830d357d3d6 (diff) | |
Connected the pipeline regs for t1 and t2 in the stat update logic. Verified functionality. Updated README after test implementation. The design now meets 100 MHz clock in Artix7 with speed grade -1.
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