Hardware implementation of the SHA-256 cryptographic hash function. The
implementation is written in Verilog 2001 compliant code. The
implementation includes a core and a wrapper that provides a 32-bit
interface for simple integration. There is also an alternative wrapper
that implements a Wishbone compliant interface.
This is a low area implementation that iterates over the rounds but
there is no sharing of operations such as adders.
The hardware implementation is complemented by a functional model
written in Python.
The W-memory scheduler is based on 16 32-bit registers. Thee registers
are loaded with the current block. After 16 rounds the contents of the
registers slide through the registers r5..r0 while the new W word is
inserted at r15 as well as being returned to the core.
Implementation results using the Altera Quartus-II v13.1 design tool.
Device: Cyclone IV E - EP4CE6F17C6
- 3765 LEs
- 1813 registers
- 76 MHz
- 66 cycles latency
Implementation results using the Altera Quartus-II v13.1 design tool.
Device: Cyclone IV GX - EP4CGX22CF19C6
- 3765 LEs
- 1813 registers
- 76 MHz
- 66 cycles latency
Implementation results using the Altera Quartus-II v13.1 design tool.
Device: Cyclone V GX - 5CGXFC7C7F23C8
- 1456 ALMs
- 1813 registers
- 78 MHz
- 66 cycles latency
- Extensive verification in physical device.
- Complete documentation.
(2014-02-22)
Redesigned the W-memory into a sliding window solution. This not only
removed 48 32-registers but also several muxes and address decoders.
The old implementation resources and performance:
- 9587 LEs
- 3349 registers
- 73 MHz
- 66 cycles latency
The new implementation resources and performance:
- 3765 LEs
- 1813 registers
- 76 MHz
- 66 cycles latency
(2014-02-19)
- The core has been added to the Cryptech repo. The core comes from
https://github.com/secworks/sha256
