README.md


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89


sha1
Introduction
Verilog implementation of the SHA-1 cryptgraphic hash function. The
functionality follows the specification in NIST FIPS 180-4.
The sha1 design is divided into the following sections.
 - src/rtl - RTL source files
 - src/tb  - Testbenches for the RTL files
 - src/model/python - Functional model written in python
 - doc/ - documentation (currently not done.)
 - toolruns/ - Where tools are supposed to be run. Includes a Makefile
   for building and simulating the design using Icarus
   Verilog.
The actual core consists of the following RTL files:
 - sha1.v
 - sha1_core.v
 - sha1_w_mem.v
The main core functionality is in the sha1_core file. The file
sha1_w_mem contains the message block memory W (see FIPS 180-4).
The top level entity is called sha1_core. The sha1_core module has wide
interfaces (512 bit block input, 160 bit digest). In order to make it
usable you probably want to wrap the core with a bus interface.
The file sha1.v contains a top level wrapper that provides a simple
interface with 32-bit data access . This interface contains mesage block
and digest registers to allow a host to load the next block while the
current block is being processed.
Implementation details
The implementation is iterative with one cycle/round. The initialization
takes one cycle. The W memory is based around a sliding window of 16
32-bit registers that are updated in sync with the round processing. The
total latency/message block is 82 cycles.
All registers have asynchronous reset.
The design has been implemented and tested on TerasIC DE0-Nano and C5G
FPGA boards.
Status
The design has been implemented and extensively been tested on TerasIC
DE0-Nano and C5G FPGA boards. The core has also been tested using SW
running on The Novena CPU talking to the core in the Xilinx Spartan-6
FPGA.
FPGA-results
Altera Cyclone FPGAs
Implementation results using Altera Quartus-II 13.1.
Altera Cyclone IV E
- EP4CE6F17C6
- 2913 LEs
- 1527 regs
- 107 MHz
Altera Cyclone IV GX
- EP4CGX22CF19C6
- 2814 LEs
- 1527 regs
- 105 MHz
Altera Cyclone V
- 5CGXFC7C7F23C8
- 1124 ALMs
- 1527 regs
- 104 MHz
Xilinx FPGAs
Implementation results using ISE 14.7.
** Xilinx Spartan-6 **
- xc6slx45-3csg324
- 1589 LUTs
- 564 Slices
- 1592 regs
- 100 MHz
TODO

Documentation