README.md


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sha1
Introduction
Verilog implementation of the SHA-1 cryptgraphic hash function. The
functionality follows the specification in NIST FIPS 180-4.
This core is based on the project at:
https://github.com/secworks/sha1
The implementation is iterative with one cycle/round. The initialization
takses one cycle. The W memory is based around a sliding window of 16
32-bit registers that are updated in sync with the round processing. The
total latency/message block is 82 cycles.
There is a top level wrapper that provides a 32-bit memory like
interface for easy integration into a System on Chip (SoC). This
interface contains mesage block and digest registers to allow a host to
load the next block while the current block is being processed.
The implementation also includes a functional model written in Python.
Implementation details
Altera Cyclone FPGAs
Implementation results using Altera Quartus-II 13.1.
Altera Cyclone IV E
- EP4CE6F17C6
- 2913 LEs
- 1527 regs
- 107 MHz
Altera Cyclone IV GX
- EP4CGX22CF19C6
- 2814 LEs
- 1527 regs
- 105 MHz
Altera Cyclone V
- 5CGXFC7C7F23C8
- 1124 ALMs
- 1527 regs
- 104 MHz
TODO

Extensive functional verification in real HW.
Add Wishbone interface.
Add results for Xilinx and possibly some other FPGA device.
Documentation

Status
(2014-02-23):
New version of the W memory module that quite drastically improves
resource utilization. And a bit better performance too. Also added some
new results for other Altera devices.
(2014-02-21):
Moved the core to Cryptech.