core/hash/sha1 - Verilog implementation of the SHA-1 cryptographic hash function

Age	Commit message (Expand)	Author
2015-03-17	Rearrange cores.	Paul Selkirk
2014-12-05	There is an END to this, according to Paul.	Joachim Strömbergson
2014-12-05	Adding a separate digiest update state.	Joachim Strömbergson
2014-11-07	Changed to asynch reset.	Joachim Strömbergson
2014-11-06	(1) Minor fixes of nits found by the verilator linter. (2) Removed trailing w...	Joachim Strömbergson
2014-04-01	Update of the Python model to support NIST dual block message test as well as...	Joachim Strömbergson
2014-03-17	Removed redundant flag reset wires.	Joachim Strömbergson
2014-03-16	Added wait to allow the ready flag to be dropped with resettable flags. Fixed...	Joachim Strömbergson
2014-03-14	Updating interface. Addding self resetting control regs. Fixing missing input...	Joachim Strömbergson
2014-02-23	Updated W memory module with new sliding window version. Updated README with ...	Joachim Strömbergson
2014-02-21	Adding all testbenches.	Joachim Strömbergson
2014-02-21	Adding all rtl source files for the sha-1 core.	Joachim Strömbergson
2014-02-21	Adding functional model in Python. Used to drive RTL development.	Joachim Strömbergson