| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-04-27 | Removed redundant FSM from the W memory. | Joachim Strömbergson | |
| 2017-12-08 | Syncecd SHA-1 core to github repo. No functional changes, but more compact ↵ | Joachim Strömbergson | |
| code and a lot of minor fixes to silence warnings. | |||
| 2015-12-13 | whack copyrights | Paul Selkirk | |
| 2014-11-06 | (1) Minor fixes of nits found by the verilator linter. (2) Removed trailing ↵ | Joachim Strömbergson | |
| whitespace. | |||
| 2014-03-16 | Added wait to allow the ready flag to be dropped with resettable flags. ↵ | Joachim Strömbergson | |
| Fixed name of clock delay parameter. | |||
| 2014-03-14 | Updating interface. Addding self resetting control regs. Fixing missing ↵ | Joachim Strömbergson | |
| input port declaration that caused errors during simulation in ModelSim. | |||
| 2014-02-23 | Updated W memory module with new sliding window version. Updated README with ↵ | Joachim Strömbergson | |
| more info. | |||
| 2014-02-21 | Adding all testbenches. | Joachim Strömbergson | |
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index : core/hash/sha1 | |
| Verilog implementation of the SHA-1 cryptographic hash function | git repositories |
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