| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2014-12-05 | Adding a separate digiest update state. | Joachim Strömbergson | |
| 2014-11-07 | Changed to asynch reset. | Joachim Strömbergson | |
| 2014-11-06 | (1) Minor fixes of nits found by the verilator linter. (2) Removed trailing ↵ | Joachim Strömbergson | |
| whitespace. | |||
| 2014-03-17 | Removed redundant flag reset wires. | Joachim Strömbergson | |
| 2014-03-14 | Updating interface. Addding self resetting control regs. Fixing missing ↵ | Joachim Strömbergson | |
| input port declaration that caused errors during simulation in ModelSim. | |||
| 2014-02-23 | Updated W memory module with new sliding window version. Updated README with ↵ | Joachim Strömbergson | |
| more info. | |||
| 2014-02-21 | Adding all rtl source files for the sha-1 core. | Joachim Strömbergson | |
 |
index : core/hash/sha1 | |
| Verilog implementation of the SHA-1 cryptographic hash function | git repositories |
| aboutsummaryrefslogtreecommitdiff |