core/hash/sha1 - Verilog implementation of the SHA-1 cryptographic hash function

Age	Commit message (Collapse)	Author
2020-05-12	Adding the functionality to extractd and set the intrnal hash state. Note: ↵HEAD master	Joachim Strömbergson
	The functionality has not yet been debugged. Need to add test case.
2020-05-12	Minor change. variable names are easier to read.	Joachim Strömbergson

2018-10-16	Added width definition to reset values as part of checking that all ↵	Joachim Strömbergson
	registers are properly reset.
2017-12-08	Syncecd SHA-1 core to github repo. No functional changes, but more compact ↵	Joachim Strömbergson
	code and a lot of minor fixes to silence warnings.
2015-12-13	whack copyrights	Paul Selkirk

2014-12-05	There is an END to this, according to Paul.	Joachim Strömbergson

2014-12-05	Adding a separate digiest update state.	Joachim Strömbergson

2014-11-07	Changed to asynch reset.	Joachim Strömbergson

2014-11-06	(1) Minor fixes of nits found by the verilator linter. (2) Removed trailing ↵	Joachim Strömbergson
	whitespace.
2014-02-23	Updated W memory module with new sliding window version. Updated README with ↵	Joachim Strömbergson
	more info.
2014-02-21	Adding all rtl source files for the sha-1 core.	Joachim Strömbergson