1 files changed, 9 insertions, 14 deletions
diff --git a/src/tb/tb_sha1_w_mem.v b/src/tb/tb_sha1_w_mem.v
index 337092d..1ee018f 100644
--- a/src/tb/tb_sha1_w_mem.v
+++ b/src/tb/tb_sha1_w_mem.v
@@ -37,11 +37,6 @@
 //
 //======================================================================
 
-//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/10ps
-
 module tb_sha1_w_mem();
 
 
@@ -69,9 +64,9 @@ module tb_sha1_w_mem();
   reg [511 : 0] tb_block;
   wire [31 : 0] tb_w;
 
-  reg [63 : 0] cycle_ctr;
-  reg [31 : 0] error_ctr;
-  reg [31 : 0] tc_ctr;
+  reg [63 : 0]  cycle_ctr;
+  reg [31 : 0]  error_ctr;
+  reg [31 : 0]  tc_ctr;
 
 
   //----------------------------------------------------------------
@@ -128,7 +123,7 @@ module tb_sha1_w_mem();
   //
   // Dump the current state of all W registers.
   //----------------------------------------------------------------
-  task dump_w_state();
+  task dump_w_state;
     begin
       $display("W state:");
 
@@ -158,7 +153,7 @@ module tb_sha1_w_mem();
   //----------------------------------------------------------------
   // reset_dut
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -171,7 +166,7 @@ module tb_sha1_w_mem();
   //----------------------------------------------------------------
   // init_sim
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       $display("*** Simulation init.");
       tb_clk     = 0;
@@ -190,7 +185,7 @@ module tb_sha1_w_mem();
   // Dump the contents of the memory by directly reading from
   // the registers in the dut, not via the read port.
   //----------------------------------------------------------------
-  task dump_mem();
+  task dump_mem;
     begin
       $display("*** Dumping memory:");
       $display("W[00] = 0x%08x", dut.w_mem[00]);
@@ -220,7 +215,7 @@ module tb_sha1_w_mem();
   // Test that W scheduling happens and work correctly.
   // Note: Currently not a self checking test case.
   //----------------------------------------------------------------
-  task test_w_schedule();
+  task test_w_schedule;
     begin
       $display("*** Test of W schedule processing. --");
       tb_block = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
@@ -242,7 +237,7 @@ module tb_sha1_w_mem();
   // Test that we can read data from all W registers.
   // Note: Currently not a self checking test case.
   //----------------------------------------------------------------
-  task test_read_w();
+  task test_read_w;
     reg [7 : 0] i;
     begin
       $display("*** Test of W read operations. --");