aboutsummaryrefslogtreecommitdiff
path: root/src/tb/tb_sha1_core.v
diff options
context:
space:
mode:
Diffstat (limited to 'src/tb/tb_sha1_core.v')
-rw-r--r--src/tb/tb_sha1_core.v118
1 files changed, 58 insertions, 60 deletions
diff --git a/src/tb/tb_sha1_core.v b/src/tb/tb_sha1_core.v
index 2247c22..17416f3 100644
--- a/src/tb/tb_sha1_core.v
+++ b/src/tb/tb_sha1_core.v
@@ -8,7 +8,7 @@
// Author: Joachim Strombergson
// Copyright (c) 2014, NORDUnet A/S
// All rights reserved.
-//
+//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
@@ -37,13 +37,8 @@
//
//======================================================================
-//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/10ps
-
module tb_sha1_core();
-
+
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
@@ -51,8 +46,8 @@ module tb_sha1_core();
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;
-
-
+
+
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
@@ -68,38 +63,38 @@ module tb_sha1_core();
wire tb_ready;
wire [159 : 0] tb_digest;
wire tb_digest_valid;
-
-
-
+
+
+
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
sha1_core dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
-
+
.init(tb_init),
.next(tb_next),
.block(tb_block),
-
+
.ready(tb_ready),
-
+
.digest(tb_digest),
.digest_valid(tb_digest_valid)
);
-
+
//----------------------------------------------------------------
// clk_gen
//
- // Clock generator process.
+ // Clock generator process.
//----------------------------------------------------------------
- always
+ always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
-
+
//----------------------------------------------------------------
// sys_monitor
@@ -113,59 +108,59 @@ module tb_sha1_core();
end
end
-
+
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
- task dump_dut_state();
+ task dump_dut_state;
begin
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
- $display("init = 0x%01x, next = 0x%01x",
+ $display("init = 0x%01x, next = 0x%01x",
dut.init, dut.next);
$display("block = 0x%0128x", dut.block);
- $display("ready = 0x%01x, valid = 0x%01x",
+ $display("ready = 0x%01x, valid = 0x%01x",
dut.ready, dut.digest_valid);
$display("digest = 0x%040x", dut.digest);
- $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x",
+ $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x",
dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg, dut.H4_reg);
$display("");
-
+
$display("Control signals and counter:");
$display("sha1_ctrl_reg = 0x%01x", dut.sha1_ctrl_reg);
- $display("digest_init = 0x%01x, digest_update = 0x%01x",
+ $display("digest_init = 0x%01x, digest_update = 0x%01x",
dut.digest_init, dut.digest_update);
- $display("state_init = 0x%01x, state_update = 0x%01x",
+ $display("state_init = 0x%01x, state_update = 0x%01x",
dut.state_init, dut.state_update);
- $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x",
+ $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x",
dut.first_block, dut.ready_flag, dut.w_init);
- $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x",
+ $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x",
dut.round_ctr_inc, dut.round_ctr_rst, dut.round_ctr_reg);
$display("");
$display("State registers:");
- $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x",
+ $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x",
dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg, dut.e_reg);
- $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x",
+ $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x",
dut.a_new, dut.b_new, dut.c_new, dut.d_new, dut.e_new);
$display("");
$display("State update values:");
- $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,",
+ $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,",
dut.state_logic.f, dut.state_logic.k, dut.state_logic.t, dut.w);
$display("");
end
endtask // dump_dut_state
-
-
+
+
//----------------------------------------------------------------
// reset_dut()
//----------------------------------------------------------------
- task reset_dut();
+ task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
@@ -174,18 +169,18 @@ module tb_sha1_core();
end
endtask // reset_dut
-
+
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
- task init_sim();
+ task init_sim;
begin
error_ctr = 0;
tc_ctr = 0;
-
+
tb_clk = 0;
tb_reset_n = 1;
@@ -195,13 +190,13 @@ module tb_sha1_core();
end
endtask // init_dut
-
+
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
- task display_test_result();
+ task display_test_result;
begin
if (error_ctr == 0)
begin
@@ -213,7 +208,7 @@ module tb_sha1_core();
end
end
endtask // display_test_result
-
+
//----------------------------------------------------------------
// wait_ready()
@@ -224,17 +219,17 @@ module tb_sha1_core();
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
- task wait_ready();
+ task wait_ready;
begin
while (!tb_ready)
begin
#(CLK_PERIOD);
-
+
end
end
endtask // wait_ready
-
+
//----------------------------------------------------------------
// single_block_test
//
@@ -253,25 +248,25 @@ module tb_sha1_core();
tb_init = 0;
wait_ready();
-
+
if (tb_digest == expected)
begin
$display("*** TC %0d successful.", tc_number);
$display("");
- end
+ end
else
begin
$display("*** ERROR: TC %0d NOT successful.", tc_number);
$display("Expected: 0x%040x", expected);
$display("Got: 0x%040x", tb_digest);
$display("");
-
+
error_ctr = error_ctr + 1;
end
end
endtask // single_block_test
-
+
//----------------------------------------------------------------
// double_block_test
//
@@ -298,7 +293,7 @@ module tb_sha1_core();
wait_ready();
db_digest1 = tb_digest;
$display("*** TC %0d first block done.", tc_number);
-
+
$display("*** TC %0d second block started.", tc_number);
tb_block = block2;
tb_next = 1;
@@ -306,12 +301,12 @@ module tb_sha1_core();
tb_next = 0;
wait_ready();
$display("*** TC %0d second block done.", tc_number);
-
+
if (db_digest1 == expected1)
begin
$display("*** TC %0d first block successful", tc_number);
$display("");
- end
+ end
else
begin
$display("*** ERROR: TC %0d first block NOT successful", tc_number);
@@ -320,12 +315,12 @@ module tb_sha1_core();
$display("");
db_error = 1;
end
-
+
if (db_digest1 == expected1)
begin
$display("*** TC %0d second block successful", tc_number);
$display("");
- end
+ end
else
begin
$display("*** ERROR: TC %0d second block NOT successful", tc_number);
@@ -341,11 +336,14 @@ module tb_sha1_core();
end
end
endtask // double_block_test
-
-
+
+
//----------------------------------------------------------------
// sha1_core_test
- // The main test functionality.
+ // The main test functionality.
+ //
+ // Test cases taken from:
+ // http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf
//----------------------------------------------------------------
initial
begin : sha1_core_test
@@ -356,14 +354,14 @@ module tb_sha1_core();
reg [159 : 0] res2_1;
reg [511 : 0] tc2_2;
reg [159 : 0] res2_2;
-
+
$display(" -- Testbench for sha1 core started --");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
-
+
// TC1: Single block message: "abc".
tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
res1 = 160'ha9993e364706816aba3e25717850c26c9cd0d89d;
@@ -373,11 +371,11 @@ module tb_sha1_core();
// "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"
tc2_1 = 512'h6162636462636465636465666465666765666768666768696768696A68696A6B696A6B6C6A6B6C6D6B6C6D6E6C6D6E6F6D6E6F706E6F70718000000000000000;
res2_1 = 160'hf4286818c37b27ae0408f581846771484a566572;
-
+
tc2_2 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0;
res2_2 = 160'h84983e441c3bd26ebaae4aa1f95129e5e54670f1;
double_block_test(2, tc2_1, res2_1, tc2_2, res2_2);
-
+
display_test_result();
$display("*** Simulation done.");
$finish;
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-08 14:07:45 +0000