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Diffstat (limited to 'src/tb/tb_sha1_core.v')
-rw-r--r--src/tb/tb_sha1_core.v38
1 files changed, 23 insertions, 15 deletions
diff --git a/src/tb/tb_sha1_core.v b/src/tb/tb_sha1_core.v
index ce837a1..c14efa5 100644
--- a/src/tb/tb_sha1_core.v
+++ b/src/tb/tb_sha1_core.v
@@ -59,7 +59,10 @@ module tb_sha1_core();
reg tb_reset_n;
reg tb_init;
reg tb_next;
+ reg tb_set;
reg [511 : 0] tb_block;
+ reg [159 : 0] tb_state_in;
+ wire [159 : 0] tb_state_out;
wire tb_ready;
wire [159 : 0] tb_digest;
wire tb_digest_valid;
@@ -70,19 +73,23 @@ module tb_sha1_core();
// Device Under Test.
//----------------------------------------------------------------
sha1_core dut(
- .clk(tb_clk),
- .reset_n(tb_reset_n),
+ .clk(tb_clk),
+ .reset_n(tb_reset_n),
- .init(tb_init),
- .next(tb_next),
+ .init(tb_init),
+ .next(tb_next),
+ .set(tb_set),
- .block(tb_block),
+ .block(tb_block),
- .ready(tb_ready),
+ .state_in(tb_state_in),
+ .state_out(tb_state_out),
- .digest(tb_digest),
- .digest_valid(tb_digest_valid)
- );
+ .ready(tb_ready),
+
+ .digest(tb_digest),
+ .digest_valid(tb_digest_valid)
+ );
//----------------------------------------------------------------
@@ -181,12 +188,13 @@ module tb_sha1_core();
error_ctr = 0;
tc_ctr = 0;
- tb_clk = 0;
- tb_reset_n = 1;
-
- tb_init = 0;
- tb_next = 0;
- tb_block = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ tb_clk = 0;
+ tb_reset_n = 1;
+ tb_init = 0;
+ tb_next = 0;
+ tb_set = 0;
+ tb_state_in = 160'h0;
+ tb_block = 512'h0;
end
endtask // init_dut