diff options
Diffstat (limited to 'src/rtl')
| -rw-r--r-- | src/rtl/sha1_core.v | 10 | ||||
| -rw-r--r-- | src/rtl/sha1_w_mem.v | 218 |
2 files changed, 162 insertions, 66 deletions
diff --git a/src/rtl/sha1_core.v b/src/rtl/sha1_core.v index be83b52..aae578c 100644 --- a/src/rtl/sha1_core.v +++ b/src/rtl/sha1_core.v @@ -120,6 +120,7 @@ module sha1_core( reg first_block; reg ready_flag; reg w_init; + reg w_next; wire w_ready; wire [31 : 0] w; @@ -131,10 +132,11 @@ module sha1_core( .clk(clk), .reset_n(reset_n), - .init(w_init), .block(block), + + .init(w_init), + .next(w_next), - .addr(round_ctr_reg), .w(w) ); @@ -365,6 +367,7 @@ module sha1_core( first_block = 0; ready_flag = 0; w_init = 0; + w_next = 0; round_ctr_inc = 0; round_ctr_rst = 0; digest_valid_new = 0; @@ -407,7 +410,8 @@ module sha1_core( begin state_update = 1; round_ctr_inc = 1; - + w_next = 1; + if (round_ctr_reg == SHA1_ROUNDS) begin sha1_ctrl_new = CTRL_DONE; diff --git a/src/rtl/sha1_w_mem.v b/src/rtl/sha1_w_mem.v index 9aaa403..7b30683 100644 --- a/src/rtl/sha1_w_mem.v +++ b/src/rtl/sha1_w_mem.v @@ -2,8 +2,9 @@ // // sha1_w_mem_reg.v // ----------------- -// The SHA-1 W memory. This memory includes functionality to -// expand the block into 80 words. +// The SHA-1 W memory. This memory is based around a sliding window +// of 16 32-bit registers that are used to create the w words +// needed by the core during the 80 rounds. // // // Author: Joachim Strombergson @@ -40,10 +41,11 @@ module sha1_w_mem( input wire clk, input wire reset_n, - input wire init, input wire [511 : 0] block, - input wire [6 : 0] addr, + input wire init, + input wire next, + output wire [31 : 0] w ); @@ -60,15 +62,30 @@ module sha1_w_mem( //---------------------------------------------------------------- // Registers including update variables and write enable. //---------------------------------------------------------------- - reg [31 : 0] w_mem [0 : 79]; - reg [31 : 0] w_mem_new; + reg [31 : 0] w_mem [0 : 15]; + reg [31 : 0] w_mem00_new; + reg [31 : 0] w_mem01_new; + reg [31 : 0] w_mem02_new; + reg [31 : 0] w_mem03_new; + reg [31 : 0] w_mem04_new; + reg [31 : 0] w_mem05_new; + reg [31 : 0] w_mem06_new; + reg [31 : 0] w_mem07_new; + reg [31 : 0] w_mem08_new; + reg [31 : 0] w_mem09_new; + reg [31 : 0] w_mem10_new; + reg [31 : 0] w_mem11_new; + reg [31 : 0] w_mem12_new; + reg [31 : 0] w_mem13_new; + reg [31 : 0] w_mem14_new; + reg [31 : 0] w_mem15_new; reg w_mem_we; reg [6 : 0] w_ctr_reg; reg [6 : 0] w_ctr_new; reg w_ctr_we; reg w_ctr_inc; - reg w_ctr_set; + reg w_ctr_rst; reg sha1_w_mem_ctrl_reg; reg sha1_w_mem_ctrl_new; @@ -80,14 +97,13 @@ module sha1_w_mem( //---------------------------------------------------------------- reg [31 : 0] w_tmp; reg [31 : 0] w_new; - reg [6 : 0] w_addr; - reg w_update; + reg mem_update; //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- - assign w = w_tmp; + assign w = w_tmp; //---------------------------------------------------------------- @@ -101,34 +117,45 @@ module sha1_w_mem( begin : reg_update if (!reset_n) begin + w_mem[00] <= 32'h00000000; + w_mem[01] <= 32'h00000000; + w_mem[02] <= 32'h00000000; + w_mem[03] <= 32'h00000000; + w_mem[04] <= 32'h00000000; + w_mem[05] <= 32'h00000000; + w_mem[06] <= 32'h00000000; + w_mem[07] <= 32'h00000000; + w_mem[08] <= 32'h00000000; + w_mem[09] <= 32'h00000000; + w_mem[10] <= 32'h00000000; + w_mem[11] <= 32'h00000000; + w_mem[12] <= 32'h00000000; + w_mem[13] <= 32'h00000000; + w_mem[14] <= 32'h00000000; + w_mem[15] <= 32'h00000000; w_ctr_reg <= 7'b0000000; sha1_w_mem_ctrl_reg <= CTRL_IDLE; end else begin - if (init) - begin - w_mem[00] <= block[511 : 480]; - w_mem[01] <= block[479 : 448]; - w_mem[02] <= block[447 : 416]; - w_mem[03] <= block[415 : 384]; - w_mem[04] <= block[383 : 352]; - w_mem[05] <= block[351 : 320]; - w_mem[06] <= block[319 : 288]; - w_mem[07] <= block[287 : 256]; - w_mem[08] <= block[255 : 224]; - w_mem[09] <= block[223 : 192]; - w_mem[10] <= block[191 : 160]; - w_mem[11] <= block[159 : 128]; - w_mem[12] <= block[127 : 96]; - w_mem[13] <= block[95 : 64]; - w_mem[14] <= block[63 : 32]; - w_mem[15] <= block[31 : 0]; - end - if (w_mem_we) begin - w_mem[w_addr] <= w_mem_new; + w_mem[00] <= w_mem00_new; + w_mem[01] <= w_mem01_new; + w_mem[02] <= w_mem02_new; + w_mem[03] <= w_mem03_new; + w_mem[04] <= w_mem04_new; + w_mem[05] <= w_mem05_new; + w_mem[06] <= w_mem06_new; + w_mem[07] <= w_mem07_new; + w_mem[08] <= w_mem08_new; + w_mem[09] <= w_mem09_new; + w_mem[10] <= w_mem10_new; + w_mem[11] <= w_mem11_new; + w_mem[12] <= w_mem12_new; + w_mem[13] <= w_mem13_new; + w_mem[14] <= w_mem14_new; + w_mem[15] <= w_mem15_new; end if (w_ctr_we) @@ -146,40 +173,105 @@ module sha1_w_mem( //---------------------------------------------------------------- - // external_addr_mux + // select_w // - // Mux for the external read operation. This is where we exract - // the W variable. + // W word selection logic. Returns either directly from the + // memory or the next w value calculated. //---------------------------------------------------------------- always @* - begin : external_addr_mux - w_tmp = w_mem[addr]; - end // external_addr_mux - + begin : w_schedule + if (w_ctr_reg < 16) + begin + w_tmp = w_mem[w_ctr_reg[3 : 0]]; + end + else + begin + w_tmp = w_new; + end + end // w_schedule + //---------------------------------------------------------------- - // w_schedule + // w_mem_update_logic // - // W word expansion logic. + // Update logic for the W memory. This is where the scheduling + // based on a sliding window is implemented. //---------------------------------------------------------------- always @* - begin : w_schedule - reg [31 : 0] w_new_tmp; + begin : w_mem_update_logic + reg [31 : 0] w_0; + reg [31 : 0] w_2; + reg [31 : 0] w_8; + reg [31 : 0] w_13; + reg [31 : 0] w_16; + + w_mem00_new = 32'h00000000; + w_mem01_new = 32'h00000000; + w_mem02_new = 32'h00000000; + w_mem03_new = 32'h00000000; + w_mem04_new = 32'h00000000; + w_mem05_new = 32'h00000000; + w_mem06_new = 32'h00000000; + w_mem07_new = 32'h00000000; + w_mem08_new = 32'h00000000; + w_mem09_new = 32'h00000000; + w_mem10_new = 32'h00000000; + w_mem11_new = 32'h00000000; + w_mem12_new = 32'h00000000; + w_mem13_new = 32'h00000000; + w_mem14_new = 32'h00000000; + w_mem15_new = 32'h00000000; + w_mem_we = 0; + + w_0 = w_mem[0]; + w_2 = w_mem[2]; + w_8 = w_mem[8]; + w_13 = w_mem[13]; + w_16 = w_13 ^ w_8 ^ w_2 ^ w_0; + w_new = {w_16[30 : 0], w_16[31]}; - w_mem_we = 0; - w_new_tmp = 32'h00000000; - w_mem_new = 32'h00000000; - w_addr = 0; + if (init) + begin + w_mem00_new = block[511 : 480]; + w_mem01_new = block[479 : 448]; + w_mem02_new = block[447 : 416]; + w_mem03_new = block[415 : 384]; + w_mem04_new = block[383 : 352]; + w_mem05_new = block[351 : 320]; + w_mem06_new = block[319 : 288]; + w_mem07_new = block[287 : 256]; + w_mem08_new = block[255 : 224]; + w_mem09_new = block[223 : 192]; + w_mem10_new = block[191 : 160]; + w_mem11_new = block[159 : 128]; + w_mem12_new = block[127 : 96]; + w_mem13_new = block[95 : 64]; + w_mem14_new = block[63 : 32]; + w_mem15_new = block[31 : 0]; + w_mem_we = 1; + end - if (w_update) + else if (w_ctr_reg > 15) begin - w_new_tmp = w_mem[(w_ctr_reg - 3)] ^ w_mem[(w_ctr_reg - 8)] ^ - w_mem[(w_ctr_reg - 14)] ^ w_mem[(w_ctr_reg - 16)]; - w_mem_new = {w_new_tmp[30 : 0], w_new_tmp[31]}; - w_addr = w_ctr_reg; - w_mem_we = 1; + w_mem00_new = w_mem[01]; + w_mem01_new = w_mem[02]; + w_mem02_new = w_mem[03]; + w_mem03_new = w_mem[04]; + w_mem04_new = w_mem[05]; + w_mem05_new = w_mem[06]; + w_mem06_new = w_mem[07]; + w_mem07_new = w_mem[08]; + w_mem08_new = w_mem[09]; + w_mem09_new = w_mem[10]; + w_mem10_new = w_mem[11]; + w_mem11_new = w_mem[12]; + w_mem12_new = w_mem[13]; + w_mem13_new = w_mem[14]; + w_mem14_new = w_mem[15]; + w_mem15_new = w_new; + w_mem_we = 1; end - end // w_schedule + end // w_mem_update_logic //---------------------------------------------------------------- @@ -193,9 +285,9 @@ module sha1_w_mem( w_ctr_new = 0; w_ctr_we = 0; - if (w_ctr_set) + if (w_ctr_rst) begin - w_ctr_new = 6'h10; + w_ctr_new = 6'h00; w_ctr_we = 1; end @@ -214,10 +306,8 @@ module sha1_w_mem( //---------------------------------------------------------------- always @* begin : sha1_w_mem_fsm - w_ctr_set = 0; - w_ctr_inc = 0; - w_update = 0; - + w_ctr_rst = 0; + w_ctr_inc = 0; sha1_w_mem_ctrl_new = CTRL_IDLE; sha1_w_mem_ctrl_we = 0; @@ -226,7 +316,7 @@ module sha1_w_mem( begin if (init) begin - w_ctr_set = 1; + w_ctr_rst = 1; sha1_w_mem_ctrl_new = CTRL_UPDATE; sha1_w_mem_ctrl_we = 1; end @@ -234,9 +324,11 @@ module sha1_w_mem( CTRL_UPDATE: begin - w_update = 1; - w_ctr_inc = 1; - + if (next) + begin + w_ctr_inc = 1; + end + if (w_ctr_reg == SHA1_ROUNDS) begin sha1_w_mem_ctrl_new = CTRL_IDLE; |