1 files changed, 3 insertions, 3 deletions
diff --git a/src/rtl/sha1_w_mem.v b/src/rtl/sha1_w_mem.v
index c91a535..cafb35c 100644
--- a/src/rtl/sha1_w_mem.v
+++ b/src/rtl/sha1_w_mem.v
@@ -109,10 +109,10 @@ module sha1_w_mem(
   // reg_update
   //
   // Update functionality for all registers in the core.
-  // All registers are positive edge triggered with synchronous
-  // active low reset. All registers have write enable.
+  // All registers are positive edge triggered with
+  // asynchronous active low reset.
   //----------------------------------------------------------------
-  always @ (posedge clk)
+  always @ (posedge clk or negedge reset_n)
     begin : reg_update
       if (!reset_n)
         begin