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-rw-r--r--src/rtl/sha1_core.v22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/rtl/sha1_core.v b/src/rtl/sha1_core.v
index d055467..9078018 100644
--- a/src/rtl/sha1_core.v
+++ b/src/rtl/sha1_core.v
@@ -44,9 +44,13 @@ module sha1_core(
input wire init,
input wire next,
+ input wire set,
input wire [511 : 0] block,
+ input wire [159 : 0] state_in,
+ output wire [159 : 0] state_out,
+
output wire ready,
output wire [159 : 0] digest,
@@ -119,6 +123,7 @@ module sha1_core(
reg digest_update;
reg init_state;
reg update_state;
+ reg set_state;
reg first_block;
reg ready_flag;
reg w_init;
@@ -146,6 +151,7 @@ module sha1_core(
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_flag;
+ assign state_out = {e_reg, d_reg, c_reg, b_reg, a_reg};
assign digest = {H0_reg, H1_reg, H2_reg, H3_reg, H4_reg};
assign digest_valid = digest_valid_reg;
@@ -321,6 +327,16 @@ module sha1_core(
e_new = d_reg;
a_e_we = 1;
end
+
+ if (set_state)
+ begin
+ a_new = state_in[031 : 000];
+ b_new = state_in[063 : 032];
+ c_new = state_in[095 : 064];
+ d_new = state_in[127 : 096];
+ e_new = state_in[159 : 128];
+ a_e_we = 1;
+ end
end // state_logic
@@ -359,6 +375,7 @@ module sha1_core(
digest_update = 0;
init_state = 0;
update_state = 0;
+ set_state = 0;
first_block = 0;
ready_flag = 0;
w_init = 0;
@@ -375,6 +392,11 @@ module sha1_core(
begin
ready_flag = 1;
+ if (set)
+ begin
+ set_state = 1'h1;
+ end
+
if (init)
begin
digest_init = 1;