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-rwxr-xr-xtoolruns/Makefile13
1 files changed, 7 insertions, 6 deletions
diff --git a/toolruns/Makefile b/toolruns/Makefile
index b11a41a..aadbb0e 100755
--- a/toolruns/Makefile
+++ b/toolruns/Makefile
@@ -8,7 +8,7 @@
# Author: Joachim Strombergson
# Copyright (c) 2014, NORDUnet A/S
# All rights reserved.
-#
+#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
@@ -47,6 +47,7 @@ TOP_SRC=../src/rtl/sha1.v $(CORE_SRC)
TOP_TB_SRC=../src/tb/tb_sha1.v
CC=iverilog
+LINT=verilator
all: top core wmem
@@ -64,6 +65,10 @@ wmem: $(WMEM_SRC) $(WMEM_TB_SRC)
$(CC) -o wmem.sim $(WMEM_SRC) $(WMEM_TB_SRC)
+lint: $(TOP_SRC)
+ verilator --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME $(TOP_SRC)
+
+
sim-top: top.sim
./top.sim
@@ -76,10 +81,6 @@ sim-wmem: wmem.sim
./wmem.sim
-debug:
- @echo "No debug available."
-
-
clean:
rm -f top.sim
rm -f core.sim
@@ -93,10 +94,10 @@ help:
@echo "top: Build the top simulation target."
@echo "core: Build the core simulation target."
@echo "wmem: Build the wmem simulation target."
+ @echo "lint: Run linter on the source files."
@echo "sim-top: Run top level simulation."
@echo "sim-core: Run core level simulation."
@echo "sim-wmem: Run wmem level simulation."
- @echo "debug: Print the internal varibles."
@echo "clean: Delete all built files."
#===================================================================