Added width definition to reset values as part of checking that all registers are properly reset.

2 files changed, 6 insertions, 6 deletions

diff --git a/src/rtl/sha1.v b/src/rtl/sha1.v
index c1fd8ec..16b565e 100644
--- a/src/rtl/sha1.v
+++ b/src/rtl/sha1.v
@@ -154,11 +154,11 @@ module sha1(
 
       if (!reset_n)
         begin
-          init_reg         <= 0;
-          next_reg         <= 0;
-          ready_reg        <= 0;
+          init_reg         <= 1'h0;
+          next_reg         <= 1'h0;
+          ready_reg        <= 1'h0;
           digest_reg       <= 160'h0;
-          digest_valid_reg <= 0;
+          digest_valid_reg <= 1'h0;
 
           for (i = 0 ; i < 16 ; i = i + 1)
             block_reg[i] <= 32'h0;
diff --git a/src/rtl/sha1_core.v b/src/rtl/sha1_core.v
index e38da3b..9a311ca 100644
--- a/src/rtl/sha1_core.v
+++ b/src/rtl/sha1_core.v
@@ -170,8 +170,8 @@ module sha1_core(
           H2_reg           <= 32'h0;
           H3_reg           <= 32'h0;
           H4_reg           <= 32'h0;
-          digest_valid_reg <= 0;
-          round_ctr_reg    <= 7'b0;
+          digest_valid_reg <= 1'h0;
+          round_ctr_reg    <= 7'h0;
           sha1_ctrl_reg    <= CTRL_IDLE;
         end
       else