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sha1

Introduction

Verilog implementation of the SHA-1 cryptgraphic hash function. The functionality follows the specification in NIST FIPS 180-4.

This core is based on the project at: https://github.com/secworks/sha1

The implementation is iterative with one cycle/round. The initialization takses one cycle. The W memory is based around a sliding window of 16 32-bit registers that are updated in sync with the round processing. The total latency/message block is 82 cycles.

There are top level wrappers that provides interface for easy integration into a System on Chip (SoC). This interface contains mesage block and digest registers to allow a host to load the next block while the current block is being processed.

The implementation also includes a functional model written in Python.

Implementation details

The sha1 design is divided into the following sections. - src/rtl - RTL source files - src/tb - Testbenches for the RTL files - src/model/python - Functional model written in python - doc - documentation (currently not done.) - toolruns - Where tools are supposed to be run. Includes a Makefile for building and simulating the design using Icarus Verilog

The actual core consists of the following files: - sha1_core.v - The core itself with wide interfaces. - sha1_w_mem.v - W message block memort and expansion logic. - sha1_k_constants.v - K constants ROM memory.

The top level entity is called sha1_core. This entity has wide interfaces (512 bit block input, 160 bit digest). In order to make it usable you probably want to wrap the core with a bus interface.

Unless you want to provide your own interface you therefore also need to select one top level wrapper. There are two wrappers provided: - sha1.v - A wrapper with a 32-bit memory like interface. - wb_sha1.v - A wrapper that implements a Wishbone interface.

Do not include both wrappers in the same project.

The core (sha1_core) will sample all data inputs when given the init or next signal. the wrappers provided contains additional data registers. This allows you to load a new block while the core is processing the previous block.

FPGA-results

Altera Cyclone FPGAs

Implementation results using Altera Quartus-II 13.1.

Altera Cyclone IV E - EP4CE6F17C6 - 2913 LEs - 1527 regs - 107 MHz

Altera Cyclone IV GX - EP4CGX22CF19C6 - 2814 LEs - 1527 regs - 105 MHz

Altera Cyclone V - 5CGXFC7C7F23C8 - 1124 ALMs - 1527 regs - 104 MHz

TODO

  • Extensive functional verification in real HW.
  • Add Wishbone interface.
  • Add results for Xilinx and possibly some other FPGA device.
  • Documentation

Status

(2013-02-25)

Updated README with some more information about the design.

(2014-02-23):

New version of the W memory module that quite drastically improves resource utilization. And a bit better performance too. Also added some new results for other Altera devices.

(2014-02-21):

Moved the core to Cryptech.