Verilog implementation of the SHA-1 cryptgraphic hash function.
The implementaion follows the specification in NIST FIPS 180-4.
This core is based on the project at:
https://github.com/secworks/sha1
Implementation results using Altera Quartus-II 13.1.
Altera Cyclone IV E
- EP4CE6F17C6
- 2913 LEs
- 1527 regs
- 107 MHz
Altera Cyclone IV GX
- EP4CGX22CF19C6
- 2814 LEs
- 1527 regs
- 105 MHz
Altera Cyclone V
- 5CGXFC7C7F23C8
- 1124 ALMs
- 1527 regs
- 104 MHz
- Extensive functional verification in real HW.
- Add Wishbone interface.
- Add results for Xilinx and possibly some other FPGA device.
- Documentation
(2014-02-23):
New version of the W memory module that quite drastically improves
resource utilization. And a bit better performance too. Also added some
new results for other Altera devices.
(2014-02-21):
Moved the core to Cryptech.
