core/hash/sha1 - Verilog implementation of the SHA-1 cryptographic hash function

Branch	Commit message	Author	Age
master	Adding the functionality to extractd and set the intrnal hash state. Note: Th...	Joachim Strömbergson	5 years


Age	Commit message	Author
2020-05-12	Adding the functionality to extractd and set the intrnal hash state. Note: Th...HEAD master	Joachim Strömbergson
2020-05-12	Minor change. variable names are easier to read.	Joachim Strömbergson
2018-10-16	Added width definition to reset values as part of checking that all registers...	Joachim Strömbergson
2018-10-03	Restricted write access for control bits to when the core is ready.	Joachim Strömbergson
2018-04-27	Removed obsolete defines.	Joachim Strömbergson
2018-04-27	Added proper cc flags and lint flags. Cleaned up rules a bit.	Joachim Strömbergson
2018-04-27	Removed redundant FSM from the W memory.	Joachim Strömbergson
2017-12-15	Removing stale wires.	Joachim Strömbergson
2017-12-15	Adding lint target.	Joachim Strömbergson
2017-12-08	Syncecd SHA-1 core to github repo. No functional changes, but more compact co...	Joachim Strömbergson
[...]

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https://git.cryptech.is/core/hash/sha1