index
:
core/comm/uart
master
A Universal asynchronous receiver/transmitter (UART) implemented in Verilog
git repositories
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
tb
Mode
Name
Size
-rw-r--r--
tb_uart.v
12848
log
plain
blame
