| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | LICENSE | 1318 | logplainblame |
| -rw-r--r-- | README.md | 171 | logplainblame |
| d--------- | src | 88 | logplain |
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index : core/comm/uart | |
| A Universal asynchronous receiver/transmitter (UART) implemented in Verilog | git repositories |
| aboutsummaryrefslogtreecommitdiff |