index
:
core/comm/uart
master
A Universal asynchronous receiver/transmitter (UART) implemented in Verilog
git repositories
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Mode
Name
Size
-rw-r--r--
LICENSE
1511
log
plain
blame
-rw-r--r--
README.md
341
log
plain
blame
d---------
src
88
log
plain
d---------
toolruns
36
log
plain