Age | Commit message (Collapse) | Author | |
---|---|---|---|
2014-03-13 | Adding Python program to test the uart. | Joachim Strömbergson | |
2014-03-13 | Adding testbench for the uart. | Joachim Strömbergson | |
2014-03-13 | Adding RTL files for the uart. | Joachim Strömbergson | |
index : core/comm/uart | ||
A Universal asynchronous receiver/transmitter (UART) implemented in Verilog | git repositories |
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Age | Commit message (Collapse) | Author | |
---|---|---|---|
2014-03-13 | Adding Python program to test the uart. | Joachim Strömbergson | |
2014-03-13 | Adding testbench for the uart. | Joachim Strömbergson | |
2014-03-13 | Adding RTL files for the uart. | Joachim Strömbergson | |