Age | Commit message (Expand) | Author |
---|---|---|
2014-03-17 | Changing from blocking to correct, non-blocking assignments in reg update. | Joachim StroĢmbergson |
2014-03-13 | Adding RTL files for the uart. | Joachim StroĢmbergson |
index : core/comm/uart | ||
A Universal asynchronous receiver/transmitter (UART) implemented in Verilog | git repositories |
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Age | Commit message (Expand) | Author |
---|---|---|
2014-03-17 | Changing from blocking to correct, non-blocking assignments in reg update. | Joachim StroĢmbergson |
2014-03-13 | Adding RTL files for the uart. | Joachim StroĢmbergson |