aboutsummaryrefslogtreecommitdiff
path: root/src/rtl
diff options
context:
space:
mode:
authorPaul Selkirk <paul@psgd.org>2015-03-31 16:26:24 -0400
committerPaul Selkirk <paul@psgd.org>2015-03-31 16:26:24 -0400
commita1fa96f258c8ef6e9046bd28fc11cf088d00e791 (patch)
tree1175191a6065dc3767409552ddb5fb7c671ac71d /src/rtl
parentfa9d69e65ce17f47a3bf84517f3fb2b38bc55575 (diff)
Don't delay register reads in uart_regs.
Diffstat (limited to 'src/rtl')
-rw-r--r--src/rtl/uart_regs.v94
1 files changed, 47 insertions, 47 deletions
diff --git a/src/rtl/uart_regs.v b/src/rtl/uart_regs.v
index 22591c4..af2ac57 100644
--- a/src/rtl/uart_regs.v
+++ b/src/rtl/uart_regs.v
@@ -45,7 +45,8 @@ module comm_regs
input wire [ 7 : 0] address,
input wire [31 : 0] write_data,
- output wire [31 : 0] read_data
+ output wire [31 : 0] read_data,
+ output wire error
);
@@ -93,53 +94,52 @@ module comm_regs
//----------------------------------------------------------------
// Access Handler
//----------------------------------------------------------------
- always @(posedge clk)
- //
- if (rst) begin
- terasic_top.bit_rate <= DEFAULT_BIT_RATE;
- terasic_top.data_bits <= DEFAULT_DATA_BITS;
- terasic_top.stop_bits <= DEFAULT_STOP_BITS;
+ always @ (posedge clk or posedge rst)
+ begin
+ if (rst)
+ begin
+ terasic_top.bit_rate <= DEFAULT_BIT_RATE;
+ terasic_top.data_bits <= DEFAULT_DATA_BITS;
+ terasic_top.stop_bits <= DEFAULT_STOP_BITS;
+ end
+ else if (cs && we)
+ begin
+ // write operations
+ case (address)
+ ADDR_BIT_RATE:
+ terasic_top.bit_rate <= write_data[15 : 0];
+ ADDR_DATA_BITS:
+ terasic_top.data_bits <= write_data[3 : 0];
+ ADDR_STOP_BITS:
+ terasic_top.stop_bits <= write_data[1 : 0];
+ endcase
+ end
end
- else if (cs) begin
- //
- if (we) begin
- //
- // WRITE handler
- //
- case (address)
- ADDR_BIT_RATE:
- terasic_top.bit_rate <= write_data[15 : 0];
- ADDR_DATA_BITS:
- terasic_top.data_bits <= write_data[3 : 0];
- ADDR_STOP_BITS:
- terasic_top.stop_bits <= write_data[1 : 0];
- endcase
- //
- end else begin
- //
- // READ handler
- //
- case (address)
- ADDR_CORE_NAME0:
- tmp_read_data = CORE_NAME0;
- ADDR_CORE_NAME1:
- tmp_read_data = CORE_NAME1;
- ADDR_CORE_TYPE:
- tmp_read_data = CORE_TYPE;
- ADDR_CORE_VERSION:
- tmp_read_data = CORE_VERSION;
- ADDR_BIT_RATE:
- tmp_read_data = {16'h0000, terasic_top.bit_rate};
- ADDR_DATA_BITS:
- tmp_read_data = {28'h0000000, terasic_top.data_bits};
- ADDR_STOP_BITS:
- tmp_read_data = {30'h0000000, terasic_top.stop_bits};
- default:
- tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
- endcase
- //
- end
- //
+
+ always @*
+ begin
+ tmp_read_data = 32'h00000000;
+
+ if (cs && !we)
+ begin
+ // read operations
+ case (address)
+ ADDR_CORE_NAME0:
+ tmp_read_data = CORE_NAME0;
+ ADDR_CORE_NAME1:
+ tmp_read_data = CORE_NAME1;
+ ADDR_CORE_TYPE:
+ tmp_read_data = CORE_TYPE;
+ ADDR_CORE_VERSION:
+ tmp_read_data = CORE_VERSION;
+ ADDR_BIT_RATE:
+ tmp_read_data = {16'h0000, terasic_top.bit_rate};
+ ADDR_DATA_BITS:
+ tmp_read_data = {28'h0000000, terasic_top.data_bits};
+ ADDR_STOP_BITS:
+ tmp_read_data = {30'h0000000, terasic_top.stop_bits};
+ endcase
+ end
end
endmodule // uart