diff options
Diffstat (limited to 'src/rtl/i2c_core.v')
| -rw-r--r-- | src/rtl/i2c_core.v | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/rtl/i2c_core.v b/src/rtl/i2c_core.v index f5d7c87..89bcba7 100644 --- a/src/rtl/i2c_core.v +++ b/src/rtl/i2c_core.v @@ -37,6 +37,12 @@ /////////// `timescale 1 ns / 1 ps +// This file is based on https://github.com/bunnie/novena-gpbb-fpga/blob/master/novena-gpbb.srcs/sources_1/imports/imports/i2c_slave.v +// +// For Cryptech, we replaced the register interface with the rxd/txd +// interface to coretest, and changed i2c_device_addr from an 8-bit +// input to a 7-bit output. + module i2c_core ( input wire clk, input wire reset, @@ -45,7 +51,7 @@ module i2c_core ( input wire SCL, input wire SDA, output reg SDA_pd, - input wire [7:0] i2c_device_addr, + output wire [6:0] i2c_device_addr, // Internal receive interface. output wire rxd_syn, @@ -139,7 +145,7 @@ module i2c_core ( assign rxd_data = I2C_wdata; assign rxd_syn = rxd_syn_reg; assign txd_ack = txd_ack_reg; - + assign i2c_device_addr = I2C_daddr[7:1]; ////////// code begins here always @ (posedge clk) begin @@ -164,9 +170,7 @@ module i2c_core ( end I2C_ACK_DADDR: begin // depending upon W/R bit state, go to one of two branches I2C_nstate = (SCL_cstate == SCL_FALL) ? - (I2C_daddr[7:1] == i2c_device_addr[7:1]) ? (I2C_daddr[0] == 1'b0 ? I2C_WR_DATA : I2C_TXD_SYN) : - I2C_WAITSTOP : // !I2C_daddr match I2C_ACK_DADDR; // !SCL_FALL end |