1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
|
`define USE_EIM
module eim
(
// EIM interface pins from CPU
input wire eim_bclk, // EIM burst clock. Started by the CPU.
input wire eim_cs0_n, // Chip select (active low).
inout wire [15 : 0] eim_da, // Bidirectional address and data port.
input wire [18: 16] eim_a, // MSB part of address port.
input wire eim_lba_n, // Latch address signal (active low).
input wire eim_wr_n, // write enable signal (active low).
input wire eim_oe_n, // output enable signal (active low).
output wire eim_wait_n, // Data wait signal (active low).
// system clock and reset
input wire sys_clk,
input wire sys_rst_n,
// EIM interface to cores
output wire [16: 0] sys_eim_addr,
output wire sys_eim_wr,
output wire sys_eim_rd,
output wire [31: 0] sys_eim_dout,
input wire [31: 0] sys_eim_din,
// Novena utility ports
output wire led_pin // LED on edge close to the FPGA.
);
//----------------------------------------------------------------
// EIM Arbiter
//
// EIM arbiter handles EIM access and transfers it into
// `sys_clk' clock domain.
//----------------------------------------------------------------
eim_arbiter eim
(
.eim_bclk(eim_bclk),
.eim_cs0_n(eim_cs0_n),
.eim_da(eim_da),
.eim_a(eim_a),
.eim_lba_n(eim_lba_n),
.eim_wr_n(eim_wr_n),
.eim_oe_n(eim_oe_n),
.eim_wait_n(eim_wait_n),
.sys_clk(sys_clk),
.sys_addr(sys_eim_addr),
.sys_wren(sys_eim_wr),
.sys_data_out(sys_eim_dout),
.sys_rden(sys_eim_rd),
.sys_data_in(sys_eim_din)
);
//----------------------------------------------------------------
// LED Driver
//
// A simple utility LED driver that turns on the Novena
// board LED when the EIM interface is active.
//----------------------------------------------------------------
eim_indicator led
(
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.eim_active(sys_eim_wr | sys_eim_rd),
.led_out(led_pin)
);
endmodule // eim
|
