| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-06-10 | change comm_regs sys_rst (unused) to reset_n for consistency with other cores | Paul Selkirk |
| 2015-04-29 | Cleanup: add error port, remove dummy register. | Paul Selkirk |
| 2015-03-31 | Don't delay register reads in eim_regs. | Paul Selkirk |
| 2015-03-17 | Rearrange cores. | Paul Selkirk |
 |
index : core/comm/eim | |
| Verilog implementation of EIM interface used to connect FPGA cores to Freescale i | git repositories |
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