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| author | Paul Selkirk <pselkirk@isc.org> | 2015-03-17 13:48:08 +0100 |
|---|---|---|
| committer | Paul Selkirk <pselkirk@isc.org> | 2015-03-17 13:48:08 +0100 |
| commit | 385984875e96f79637d8b6a5de1225536acd94a1 (patch) | |
| tree | 89667e4b2d60b5648f7822452c725e27f597712c | |
| parent | 9d6183bcd6e0437151839d640ba74d72240b40e1 (diff) | |
Rearrange cores.
| -rw-r--r-- | src/rtl/coretest.v | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/rtl/coretest.v b/src/rtl/coretest.v index 1886cd4..918312d 100644 --- a/src/rtl/coretest.v +++ b/src/rtl/coretest.v @@ -113,7 +113,8 @@ module coretest( parameter TEST_RST_END = 8'h32; parameter TEST_RD_START = 8'h50; parameter TEST_RD_WAIT = 8'h51; - parameter TEST_RD_END = 8'h52; + parameter TEST_RD_WAIT2 = 8'h52; + parameter TEST_RD_END = 8'h53; parameter TEST_WR_START = 8'h60; parameter TEST_WR_WAIT = 8'h61; parameter TEST_WR_END = 8'h62; @@ -1080,6 +1081,13 @@ module coretest( TEST_RD_WAIT: begin + test_engine_new = TEST_RD_WAIT2; + test_engine_we = 1; + end + + + TEST_RD_WAIT2: + begin sample_core_output = 1; test_engine_new = TEST_RD_END; test_engine_we = 1; |