Update of testbench with monitor for test core access, new test cases etc.

1 files changed, 166 insertions, 36 deletions

diff --git a/src/tb/tb_coretest.v b/src/tb/tb_coretest.v
index 30d2177..e70770d 100644
--- a/src/tb/tb_coretest.v
+++ b/src/tb/tb_coretest.v
@@ -6,7 +6,8 @@
 //
 //
 // Author: Joachim Strombergson
-// Copyright (c) 2014 SUNET
+// Copyright (c) 2014, SUNET
+// All rights reserved.
 // 
 // Redistribution and use in source and binary forms, with or 
 // without modification, are permitted provided that the following 
@@ -48,17 +49,29 @@ module tb_coretest();
   //----------------------------------------------------------------
   parameter DEBUG           = 0;
   parameter VERBOSE         = 0;
+  parameter CMD_MONITOR     = 1;
+  parameter REC_MONITOR     = 0;
 
   parameter CLK_HALF_PERIOD = 1;
   parameter CLK_PERIOD      = CLK_HALF_PERIOD * 2;
-  
 
-  parameter SOF = 8'h55;
-  parameter EOF = 8'haa;
-  parameter OP_RESET = 8'h01;
-  parameter OP_READ  = 8'h10;
-  parameter OP_WRITE = 8'h11;
+  // Command and response constants.
+  parameter SOC       = 8'h55;
+  parameter EOC       = 8'haa;
+  parameter RESET_CMD = 8'h01;
+  parameter READ_CMD  = 8'h10; 
+  parameter WRITE_CMD = 8'h11; 
+
+  parameter SOR      = 8'haa;
+  parameter EOR      = 8'h55;
+  parameter UNKNOWN  = 8'hfe;
+  parameter ERROR    = 8'hfd;
+  parameter READ_OK  = 8'h7f;
+  parameter WRITE_OK = 8'h7e;
+  parameter RESET_OK = 8'h7d;
   
+  parameter MAX_MEM  = 16'h00ff;
+
   
   //----------------------------------------------------------------
   // Register and Wire declarations.
@@ -87,7 +100,8 @@ module tb_coretest();
 
   reg [7 : 0]   received_tx_data;
   
-  
+  reg [31 : 0]  test_mem [0 : (MAX_MEM - 1'b1)];
+
 
   //----------------------------------------------------------------
   // Device Under Test.
@@ -115,11 +129,6 @@ module tb_coretest();
                .core_error(tb_core_error)
               );
 
-  
-  //----------------------------------------------------------------
-  // Concurrent assignments.
-  //----------------------------------------------------------------
-  
 
   //----------------------------------------------------------------
   // clk_gen
@@ -130,16 +139,20 @@ module tb_coretest();
     begin : clk_gen
       #CLK_HALF_PERIOD tb_clk = !tb_clk;
     end // clk_gen
-    
 
+  
   //----------------------------------------------------------------
   // sys_monitor
+  //
+  // System monitor. Can display status about the dut and TB
+  // every cycle.
   //----------------------------------------------------------------
   always
     begin : sys_monitor
       #(CLK_PERIOD);      
       if (DEBUG)
         begin
+          dump_dut_state();
           $display("");
         end
 
@@ -149,7 +162,113 @@ module tb_coretest();
         end
       cycle_ctr = cycle_ctr + 1;
     end
+  
+
+  //----------------------------------------------------------------
+  // command_monitor
+  //
+  // Observes any read/write or reset commands generated
+  // by the DUT.
+  //----------------------------------------------------------------
+  always
+    begin : command_monitor
+      #(CLK_PERIOD);      
+      if (CMD_MONITOR)
+        begin
+          if (!tb_core_reset_n)
+            begin
+              $display("Core is being reset by coretest.");
+            end
+
+          if (tb_core_cs)
+            begin
+              if (tb_core_we)
+                begin
+                  $display("Core is being written to: address 0x%08x = 0x%08x",
+                           tb_core_address, tb_core_write_data);
+                end
+              else
+                begin
+                  $display("Core is being read from: address 0x%08x = 0x%08x",
+                           tb_core_address, tb_core_read_data);
+                end
+            end
+        end
+    end
+
 
+  //----------------------------------------------------------------
+  // receive_logic
+  //
+  // The logic needed to the correct handshake expected by the DUT
+  // when it is sending bytes.
+  //----------------------------------------------------------------
+  always @ (posedge tb_clk)
+    begin : receive_logic
+      if (tb_tx_syn)
+        begin
+          if (REC_MONITOR)
+            begin
+              $display("Receiving byte 0x%02x from the DUT.", tb_tx_data);
+            end
+          #(2 * CLK_PERIOD);
+          tb_tx_ack = 1;
+
+          #(2 * CLK_PERIOD);
+          tb_tx_ack = 0;
+        end
+    end // receive_logic
+
+
+  //----------------------------------------------------------------
+  // test_mem_logic
+  //
+  // The logic needed to implement the test memory. We basically
+  // implement a simple memory to allow read and write operations
+  // via commands to the DUT to really be executed.
+  //----------------------------------------------------------------
+  always @ (posedge tb_clk)
+    begin : test_mem_logic
+      if (tb_core_cs)
+        begin
+          if (tb_core_we)
+            begin
+              if (tb_core_address < MAX_MEM)
+                begin
+                  $display("Writing to test_mem[0x%08x] = 0x%08x",
+                           tb_core_address, tb_core_write_data);
+                  test_mem[tb_core_address] = tb_core_write_data;
+                end
+              else
+                begin
+                  $display("Writing to incorrect address 0x%08x",
+                           tb_core_address);
+                  tb_core_error = 1;
+                end
+            end
+          else
+            begin
+              if (tb_core_address < MAX_MEM)
+                begin
+                  $display("Reading from test_mem[0x%08x] = 0x%08x",
+                           tb_core_address, tb_core_read_data);
+                  tb_core_read_data = test_mem[tb_core_address];
+                end
+              else
+                begin
+                  $display("Reading from incorrect address 0x%08x",
+                           tb_core_address);
+                  tb_core_error = 1;
+                end
+            end
+        end
+      else
+        begin
+          tb_core_read_data = 32'h00000000;
+          tb_core_error     = 0;
+        end
+    end
+  
   
   //----------------------------------------------------------------
   // dump_dut_state()
@@ -169,9 +288,14 @@ module tb_coretest();
                dut.core_cs, dut.core_we, dut.core_address, dut.core_write_data, dut.core_read_data, dut.core_error);
       $display("");
 
+      $display("RX chain signals:");
+      $display("rx_buffer_wr_ptr = 0x%02x, rx_buffer_rd_ptr = 0x%02x, rx_buffer_ctr = 0x%02x, rx_buffer_empty = 0x%01x,  rx_buffer_full = 0x%01x",
+               dut.rx_buffer_wr_ptr_reg, dut.rx_buffer_rd_ptr_reg,  dut.rx_buffer_ctr_reg, dut.rx_buffer_empty, dut.rx_buffer_full);
+      $display("");
+
       $display("Control signals and FSM state:");
-      $display("test_engine_reg = 0x%02x, cmd_reg = 0x%02x, rx_buffer_ptr = 0x%02x, tx_buffer_ptr = 0x%02x",
-               dut.test_engine_reg, dut.cmd_reg, dut.rx_buffer_ptr_reg, dut.tx_buffer_ptr_reg);
+      $display("test_engine_reg = 0x%02x, cmd_reg = 0x%02x",
+               dut.test_engine_reg, dut.cmd_reg);
       $display("");
     end
   endtask // dump_dut_state
@@ -197,6 +321,8 @@ module tb_coretest();
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
   task init_sim();
+    reg [8 : 0] i;
+    
     begin
       cycle_ctr         = 0;
       error_ctr         = 0;
@@ -206,9 +332,12 @@ module tb_coretest();
       tb_reset_n        = 1;
       tb_rx_syn         = 0;
       tb_rx_data        = 8'h00;
-      tb_tx_ack         = 1;
-      tb_core_read_data = 32'h00000000;
-      tb_core_error     = 0;
+      tb_tx_ack         = 0;
+
+      for (i = 0 ; i < 256 ; i = i + 1)
+        begin
+          test_mem[i[7 : 0]] = {4{i[7 : 0]}};
+        end
     end
   endtask // init_sim
 
@@ -221,10 +350,10 @@ module tb_coretest();
   task send_byte(input [7 : 0] data);
     integer i;
     begin
-      $display("*** Sending byte 0x%02x to the dut.", data);
 
       if (VERBOSE)
         begin
+          $display("*** Sending byte 0x%02x to the dut.", data);
           $display("*** Setting RX data and RX SYN.");
         end
       tb_rx_data = data;
@@ -258,27 +387,27 @@ module tb_coretest();
   task send_reset_command();
     begin
       $display("*** Sending reset command.");
-      send_byte(SOF);
-      send_byte(OP_RESET);
-      send_byte(EOF);
+      send_byte(SOC);
+      send_byte(RESET_CMD);
+      send_byte(EOC);
       $display("*** Sending reset command done.");
     end
   endtask // send_write_command
 
   
   //----------------------------------------------------------------
-  // send_write_command
+  // send_read_command
   //
   // Generates a read command to the dut.
   //----------------------------------------------------------------
   task send_read_command(input [15 : 0] addr);
     begin
       $display("*** Sending read command: address 0x%04x.", addr);
-      send_byte(SOF);
-      send_byte(OP_READ);
+      send_byte(SOC);
+      send_byte(READ_CMD);
       send_byte(addr[15 : 8]);
       send_byte(addr[7 : 0]);
-      send_byte(EOF);
+      send_byte(EOC);
       $display("*** Sending read command done.");
     end
   endtask // send_write_command
@@ -292,15 +421,15 @@ module tb_coretest();
   task send_write_command(input [15 : 0] addr, input [31 : 0] data);
     begin
       $display("*** Sending write command: address 0x%04x = 0x%08x.", addr, data);
-      send_byte(SOF);
-      send_byte(OP_WRITE);
+      send_byte(SOC);
+      send_byte(WRITE_CMD);
       send_byte(addr[15 : 8]);
       send_byte(addr[7 : 0]);
       send_byte(data[31 : 24]);
       send_byte(data[23 : 16]);
       send_byte(data[15 : 8]);
       send_byte(data[7 : 0]);
-      send_byte(EOF);
+      send_byte(EOC);
       $display("*** Sending write command done.");
     end
   endtask // send_write_command
@@ -341,15 +470,16 @@ module tb_coretest();
       #(64 * CLK_PERIOD);
 
       send_reset_command();
-//      dump_dut_state();
 
-      send_read_command(16'h0123);
-//      dump_dut_state();
+      send_read_command(16'h0023);
+      send_read_command(16'h0055);
 
-      send_write_command(16'h4224, 32'h1337beef);
-//      dump_dut_state();
+      send_write_command(16'h00aa, 32'h1337beef);
+      send_read_command(16'h00aa);
+      send_write_command(16'h0010, 32'h55aa55aa);
+      send_read_command(16'h0010);
 
-      #(64 * CLK_PERIOD);
+      #(200 * CLK_PERIOD);
 
       display_test_result();
       $display("*** Simulation done.");