diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/rtl/aes_core.v | 14 | ||||
| -rw-r--r-- | src/rtl/aes_encipher_block.v | 3 |
2 files changed, 0 insertions, 17 deletions
diff --git a/src/rtl/aes_core.v b/src/rtl/aes_core.v index b74fdc4..518b20f 100644 --- a/src/rtl/aes_core.v +++ b/src/rtl/aes_core.v @@ -85,8 +85,6 @@ module aes_core( //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- - reg init_state; - wire [127 : 0] round_key; wire key_ready; @@ -104,10 +102,6 @@ module aes_core( reg [3 : 0] muxed_round_nr; reg muxed_ready; - wire [31 : 0] keymem_sboxw; - - wire [31 : 0] new_sboxw; - //---------------------------------------------------------------- // Instantiations. @@ -235,7 +229,6 @@ module aes_core( //---------------------------------------------------------------- always @* begin : aes_core_ctrl - init_state = 1'b0; ready_new = 1'b0; ready_we = 1'b0; result_valid_new = 1'b0; @@ -248,7 +241,6 @@ module aes_core( begin if (init) begin - init_state = 1'b1; ready_new = 1'b0; ready_we = 1'b1; result_valid_new = 1'b0; @@ -258,7 +250,6 @@ module aes_core( end else if (next) begin - init_state = 1'b0; ready_new = 1'b0; ready_we = 1'b1; result_valid_new = 1'b0; @@ -270,8 +261,6 @@ module aes_core( CTRL_INIT: begin - init_state = 1'b1; - if (key_ready) begin ready_new = 1'b1; @@ -283,8 +272,6 @@ module aes_core( CTRL_NEXT: begin - init_state = 1'b0; - if (muxed_ready) begin ready_new = 1'b1; @@ -298,7 +285,6 @@ module aes_core( default: begin - end endcase // case (aes_core_ctrl_reg) diff --git a/src/rtl/aes_encipher_block.v b/src/rtl/aes_encipher_block.v index c4440d7..f0e42f9 100644 --- a/src/rtl/aes_encipher_block.v +++ b/src/rtl/aes_encipher_block.v @@ -185,7 +185,6 @@ module aes_encipher_block( // Wires. //---------------------------------------------------------------- reg [2 : 0] update_type; - reg [31 : 0] muxed_sboxw; reg [31 : 0] sboxw0; reg [31 : 0] sboxw1; @@ -201,7 +200,6 @@ module aes_encipher_block( // Concurrent connectivity for ports etc. //---------------------------------------------------------------- assign round = round_ctr_reg; - assign sboxw = muxed_sboxw; assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg}; assign ready = ready_reg; @@ -271,7 +269,6 @@ module aes_encipher_block( reg [127 : 0] addkey_init_block, addkey_main_block, addkey_final_block; block_new = 128'h0; - muxed_sboxw = 32'h0; block_w0_we = 1'b0; block_w1_we = 1'b0; block_w2_we = 1'b0; |