diff options
Diffstat (limited to 'src/rtl')
| -rw-r--r-- | src/rtl/aes_core.v | 26 | ||||
| -rw-r--r-- | src/rtl/aes_encipher_block.v | 3 |
2 files changed, 1 insertions, 28 deletions
diff --git a/src/rtl/aes_core.v b/src/rtl/aes_core.v index 5196a1f..7c5720d 100644 --- a/src/rtl/aes_core.v +++ b/src/rtl/aes_core.v @@ -94,7 +94,6 @@ module aes_core( wire [3 : 0] enc_round_nr; wire [127 : 0] enc_new_block; wire enc_ready; - wire [31 : 0] enc_sboxw; reg dec_next; wire [3 : 0] dec_round_nr; @@ -107,7 +106,6 @@ module aes_core( wire [31 : 0] keymem_sboxw; - reg [31 : 0] muxed_sboxw; wire [31 : 0] new_sboxw; @@ -124,9 +122,6 @@ module aes_core( .round(enc_round_nr), .round_key(round_key), - .sboxw(enc_sboxw), - .new_sboxw(new_sboxw), - .block(block), .new_block(enc_new_block), .ready(enc_ready) @@ -166,7 +161,7 @@ module aes_core( ); - aes_sbox sbox_inst(.sboxw(muxed_sboxw), .new_sboxw(new_sboxw)); + aes_sbox sbox_inst(.sboxw(keymem_sboxw), .new_sboxw(new_sboxw)); //---------------------------------------------------------------- @@ -207,25 +202,6 @@ module aes_core( //---------------------------------------------------------------- - // sbox_mux - // - // Controls which of the encipher datapath or the key memory - // that gets access to the sbox. - //---------------------------------------------------------------- - always @* - begin : sbox_mux - if (init_state) - begin - muxed_sboxw = keymem_sboxw; - end - else - begin - muxed_sboxw = enc_sboxw; - end - end // sbox_mux - - - //---------------------------------------------------------------- // encdex_mux // // Controls which of the datapaths that get the next signal, have diff --git a/src/rtl/aes_encipher_block.v b/src/rtl/aes_encipher_block.v index c3e672c..c4440d7 100644 --- a/src/rtl/aes_encipher_block.v +++ b/src/rtl/aes_encipher_block.v @@ -49,9 +49,6 @@ module aes_encipher_block( output wire [3 : 0] round, input wire [127 : 0] round_key, - output wire [31 : 0] sboxw, - input wire [31 : 0] new_sboxw, - input wire [127 : 0] block, output wire [127 : 0] new_block, output wire ready |