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authorJoachim StroĢˆmbergson <joachim@secworks.se>2018-05-26 13:26:20 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2018-05-26 13:26:20 +0200
commitc1225cb6c9843e91f3b3dfee294fc1f9309e8212 (patch)
treee6d34e55e9efc60ebae31d4f0818b3ae64a5641a /README.md
parent6a39d877e450269fb216129bad8cafb7caba8a5d (diff)
Shaved off another cycle for block processing.
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@@ -40,17 +40,17 @@ Number of cycles for the old Cryptech AES core:
- AES-256 Decipher one block with key expansion: 77
Number of cycles for the Cryptech AES speed core:
-- AES-128 Encipher one block with key expansion: 17
-- AES-255 Decipher one block with key expansion: 21
+- AES-128 Encipher one block with key expansion: 16
+- AES-255 Decipher one block with key expansion: 20
## Implementation comparison
Implementation results for Xilinx Artix7-t200.
Old Cryptech AES core:
-- 2102 slices
-- 2991 regs
-- 113 MHz (8.79ns)
+- 2094 slices
+- 2854 regs
+- 114 MHz (8.76ns)
Cryptec AES speed core: