core/cipher/aes - Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard)

Age	Commit message (Collapse)	Author
2017-12-06	Synced AES repo. This commit fixes many nits such as: (1) Silence warnings ↵api_error_fix	Joachim Strömbergson
	on size of contants. (2) warning on tasks for empty arguments in tasks. (3) timescale directives not needed. It also implements API in a code-wise more compact way. Info about implementation status updated. No changes affect the functionality of the core.
2016-03-10	Fixed minor nits in names of config bits.	Joachim Strömbergson

2015-10-02	Removed unnedded code blocks.	Joachim Strömbergson

2015-10-02	Removed api error port and added error bit in status register that is set ↵	Joachim Strömbergson
	when api access violations happens and cleared by writing the status register.
2015-10-02	Fixing text error in comment.	Joachim Strömbergson

2015-07-17	fix CORE_VERSION to match what we think it should be	Paul Selkirk

2015-05-28	Corrected where config bits are.	Joachim Strömbergson

2015-05-16	(1) Changed name and version to reflect that it is not only AES-128 and that ↵	Joachim Strömbergson
	the core is fairly close to done. (2) Moved counter update.
2015-05-04	(1) Changed ordet of status and config addresses to conform to what we have ↵	Joachim Strömbergson
	in other cores. (2) Changed to localparam to stop polluting namespace.
2014-11-28	Reworked the sbox and inverse sbox. Slighly smaller design and much shorter ↵	Joachim Strömbergson
	source files.
2014-11-27	Adding Python models for AES as well as key expansion and rcon.	Joachim Strömbergson

2014-11-27	Adding testbenchs.	Joachim Strömbergson

2014-11-27	Adding RTL source files for the AES core.	Joachim Strömbergson