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Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard)
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2018-05-21
Cleaned up redundant wires.
Joachim Strömbergson
2018-05-21
Moved the Sbox used for key expansion into the key_mem.
Joachim Strömbergson
2018-05-21
Removed the sbox word mux. Removed ports for sbox access in the encipher data...
Joachim Strömbergson
2018-05-21
Removed the sword counter since it is not needed.
Joachim Strömbergson
2018-05-21
Connected the new S-boxes and collapsed the SubBytes operation into one cycle...
Joachim Strömbergson
2018-05-21
Adding 16 S-boxes to the encipher datapath.
Joachim Strömbergson
2017-12-15
Adding the error port that went missing. Sloppy.
Joachim Strömbergson
2017-12-14
Synced the AES core rtl and testbench to github. The updates does not add or ...
Joachim Strömbergson
2015-12-13
whack copyrights
Paul Selkirk
2015-10-02
Fixing text error in comment.
Joachim Strömbergson
2015-07-17
fix CORE_VERSION to match what we think it should be
Paul Selkirk
2015-05-16
(1) Changed name and version to reflect that it is not only AES-128 and that ...
Joachim Strömbergson
2015-05-04
(1) Changed ordet of status and config addresses to conform to what we have i...
Joachim Strömbergson
2014-11-28
Reworked the sbox and inverse sbox. Slighly smaller design and much shorter s...
Joachim Strömbergson
2014-11-27
Adding RTL source files for the AES core.
Joachim Strömbergson