| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-09-27 | Added missing reset of registers. This fixes CT-01-001 FPGA. | Joachim Strömbergson |
| 2018-05-21 | Moved the Sbox used for key expansion into the key_mem. | Joachim Strömbergson |
| 2017-12-14 | Synced the AES core rtl and testbench to github. The updates does not add or ... | Joachim Strömbergson |
| 2015-12-13 | whack copyrights | Paul Selkirk |
| 2014-11-27 | Adding RTL source files for the AES core. | Joachim Strömbergson |
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index : core/cipher/aes | |
| Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) | git repositories |
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