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Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard)
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aes_encipher_block.v
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2018-05-22
Minor cleanup of states and register sizes.
Joachim Strömbergson
2018-05-22
Combined all AES round operations into a single operation for a round.
Joachim Strömbergson
2018-05-21
Cleaned up redundant wires.
Joachim Strömbergson
2018-05-21
Removed the sbox word mux. Removed ports for sbox access in the encipher ↵
Joachim Strömbergson
datapath since it now has its own sboxes.
2018-05-21
Removed the sword counter since it is not needed.
Joachim Strömbergson
2018-05-21
Connected the new S-boxes and collapsed the SubBytes operation into one ↵
Joachim Strömbergson
cycle. This provides a speedup for Encipher with 2.1x.
2018-05-21
Adding 16 S-boxes to the encipher datapath.
Joachim Strömbergson
2017-12-14
Synced the AES core rtl and testbench to github. The updates does not add or ↵
Joachim Strömbergson
modify any functionality, but silence a lot of warnings, reduce code size.
2015-12-13
whack copyrights
Paul Selkirk
2014-11-27
Adding RTL source files for the AES core.
Joachim Strömbergson